FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-06-2004, 03:36 PM
jc
Guest
 
Posts: n/a
Default Xilinx Virtex II Output Register

I have a input signal thats get registered and then outputed on
another signal (pad) One register delay. I would like the Output
register to used instead of the Input register. I am using Xilinx ISE,
VHDL and a Virtex II device. Everytime I implement the Input register
is used, how do I use the Output register. I am trying to improve the
clock to pad time.

Thanks
John C
Reply With Quote
  #2 (permalink)  
Old 01-06-2004, 05:51 PM
Brannon King
Guest
 
Posts: n/a
Default Re: Xilinx Virtex II Output Register

Set IOB=FALSE on the input instance name and IOB=TRUE on the output instance
name, or use the primitives IBUF for the input buffer and OFDXI for the
output.


"jc" <[email protected]> wrote in message
news:[email protected] om...
> I have a input signal thats get registered and then outputed on
> another signal (pad) One register delay. I would like the Output
> register to used instead of the Input register. I am using Xilinx ISE,
> VHDL and a Virtex II device. Everytime I implement the Input register
> is used, how do I use the Output register. I am trying to improve the
> clock to pad time.
>
> Thanks
> John C



Reply With Quote
  #3 (permalink)  
Old 01-09-2004, 07:47 PM
Bret Wade
Guest
 
Posts: n/a
Default Re: Xilinx Virtex II Output Register

[email protected] (jc) wrote in message news:<[email protected] com>...
> I have a input signal thats get registered and then outputed on
> another signal (pad) One register delay. I would like the Output
> register to used instead of the Input register. I am using Xilinx ISE,
> VHDL and a Virtex II device. Everytime I implement the Input register
> is used, how do I use the Output register. I am trying to improve the
> clock to pad time.
>
> Thanks
> John C


John,

Since this is a Virtex-II device and you already have IOB FFs enabled,
all you need to do is add a BEL constraint to OFF1 or OFF2:

INST "FF_Name" BEL = OFF1 ;

IOB BEL constraints aren't supported for architectures older than
Virtex-II, so for a Virtex-E design, one of the following map
constraints could be used:

1. Give FF and output pad the same BLKNM constraint.
2. Give FF and output pad the same LOC constraint.
3. Apply a KEEP constraint to the FF D input net, assuming fanout of
1.

Regards,
Bret
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Re: Xilinx virtex II DCM CLKFX output not working Martin Euredjian FPGA 0 08-10-2003 08:54 AM
Re: Xilinx virtex II DCM CLKFX output not working Bob FPGA 0 08-10-2003 05:55 AM


All times are GMT +1. The time now is 02:56 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved