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  #1 (permalink)  
Old 11-14-2007, 04:15 PM
Andrew Ganger
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Default Xilinx Virtex-II Newbie

Hello,

I am in some way a newbie in getting things to run on an FGPA, so I
would be helpful if someone could help me a little bit out how to get
started.

I have implemented a simple processor architecture in VHDL and I
successfully simulated it with Modelsim. Now my next goal would be
to get this processor running on a Xilinx Virtex-II PMC FPGA board.

For synthesis I am going to use Xilinx ISE 7.1i. So to see if the
processor on the FPGA is doing what it should do I could use Chipscope
and the Jtag interface. However, I am a little bit lost with the
following tasks.

1) I had some kind for simple RAM for simulation. How can I implement
this RAM correctly so that it be sythesizable and will correctly run on
the FPGA?

2) When I start the processor, I should have my instructions loaded into
the Instruction RAM? How can I do this, really no clue

I am sorry for these basis questions, but I would be thankful if someone
could give me a hint where and how to start!

Many thanks!!
Andi


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  #2 (permalink)  
Old 11-14-2007, 04:48 PM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> 1) I had some kind for simple RAM for simulation. How can I implement
> this RAM correctly so that it be sythesizable and will correctly run on
> the FPGA?
>
> 2) When I start the processor, I should have my instructions loaded into
> the Instruction RAM? How can I do this, really no clue


I am just reading the XST userguide. There it says that with version
8.1i it is possible to directly specify data with the RAM module or
load it from an external source. IN addition it says the multiple write
ports in the RAM are supported from version 8.1 on. UNfortuantely I just
have version 7.1 and I should have a RAM that has 4 read ports and 2
write ports? Is that somehow to realise with ISE 7.1 or do I need to
upgrade to version 8.1?

Many thanks,
Andrew

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  #3 (permalink)  
Old 11-14-2007, 06:02 PM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie

Andrew Ganger wrote:
> UNfortuantely I just
> have version 7.1 and I should have a RAM that has 4 read ports and 2
> write ports? Is that somehow to realise with ISE 7.1 or do I need to
> upgrade to version 8.1?


Mixed something up, my Register File should have 4 read ports and two
write ports
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  #4 (permalink)  
Old 11-14-2007, 06:19 PM
Nathan Bialke
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Default Re: Xilinx Virtex-II Newbie

What you are asking for is outside the abilities of the Virtex-II
FPGA. Since the FPGA only contains dual-ported memories (either
SelectRAM-based or BlockRAM-based), there is no possible way to map
such a HDL description to the FPGA device.

You'll have to figure out a mechanism to multiplex the read/write
ports such that you have less than or equal to two ports (be they
read, write, or read/write ports).

Good luck - welcome to the world of FPGA engineering.

- Nathan

On Nov 14, 10:02 am, Andrew Ganger <[email protected]> wrote:
> Andrew Ganger wrote:
> > UNfortuantely I just
> > have version 7.1 and I should have a RAM that has 4 read ports and 2
> > write ports? Is that somehow to realise with ISE 7.1 or do I need to
> > upgrade to version 8.1?

>
> Mixed something up, my Register File should have 4 read ports and two
> write ports


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  #5 (permalink)  
Old 11-14-2007, 10:49 PM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> What you are asking for is outside the abilities of the Virtex-II
> FPGA. Since the FPGA only contains dual-ported memories (either
> SelectRAM-based or BlockRAM-based), there is no possible way to map
> such a HDL description to the FPGA device.


Thanks for your answer Nathan, so I cant have a register file that has 4
read ports and 2 write ports with a Virtex II? Well, unfortunately I
need these number of ports else my ISA is not working. Perhaps do you
know any FPGA boards that support Register Files which would allow such
a design as I have it? Would be very thankful for feedback!

Cheers
Andrew
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  #6 (permalink)  
Old 11-14-2007, 10:55 PM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> Are you sure that you need 4 read and 2 write ports? Do you need to
> assign the data read at the time - at the same clock edge? In that
> case you could just assign the same data read to multiple signals.
>
> How big is your register file?


Thanks for your answer Dan, I need a data and instruction RAM with one
read/write port each but I would need a register file with 4 read ports
and 2 write ports. Is such a thing feasable with Virtex II? If not, are
there any FPGA Boards that would support 4 Read Ports and 2 Write Ports
Register Files? The register File itself contains 16 registers, each of
32bits.And in the worst case it can happen that at the same clock cycle
I have to read 4 registers and to write back 2 values.

Cheers,
Andrew
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  #7 (permalink)  
Old 11-14-2007, 11:25 PM
EEngineer
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Default Re: Xilinx Virtex-II Newbie

On Nov 14, 11:15 am, Andrew Ganger <[email protected]> wrote:
> Hello,
>
> I am in some way a newbie in getting things to run on an FGPA, so I
> would be helpful if someone could help me a little bit out how to get
> started.
>
> I have implemented a simple processor architecture in VHDL and I
> successfully simulated it with Modelsim. Now my next goal would be
> to get this processor running on a Xilinx Virtex-II PMC FPGA board.
>
> For synthesis I am going to use Xilinx ISE 7.1i. So to see if the
> processor on the FPGA is doing what it should do I could use Chipscope
> and the Jtag interface. However, I am a little bit lost with the
> following tasks.
>
> 1) I had some kind for simple RAM for simulation. How can I implement
> this RAM correctly so that it be sythesizable and will correctly run on
> the FPGA?
>
> 2) When I start the processor, I should have my instructions loaded into
> the Instruction RAM? How can I do this, really no clue
>
> I am sorry for these basis questions, but I would be thankful if someone
> could give me a hint where and how to start!
>
> Many thanks!!
> Andi


Are you sure that you need 4 read and 2 write ports? Do you need to
assign the data read at the time - at the same clock edge? In that
case you could just assign the same data read to multiple signals.

How big is your register file? You may create an vhdl component that
includes an array of registers (check how to create arrays of signals
it is pretty straightforward). With a process inside this component
you can assign values to this array where the index of the array
represents the location of the register in the register file (address
input of the component). You can create another process for reading
that can use same or different clock (of different phase) for reading
of this array using the input address as an index again.

Within this component you can also manually specified the initial
values of those registers.

This way you can also create an instruction memory that contains some
array of instructions - these instructions you would also need to
specify manually within the vhdl code.

Chipscope with Jtag interface you can use to probe any signals within
the FPGA when it is configured. This way you can also read the
register file or memory that you created in VHDL.

Hope that this helps,
Dan

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  #8 (permalink)  
Old 11-15-2007, 12:45 AM
Nathan Bialke
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Default Re: Xilinx Virtex-II Newbie

I know of no tools or FPGAs that currently support inference or
instantiation of 4-ported memory.

Sorry.

On Nov 14, 2:49 pm, Andrew Ganger <[email protected]> wrote:
> > What you are asking for is outside the abilities of the Virtex-II
> > FPGA. Since the FPGA only contains dual-ported memories (either
> > SelectRAM-based or BlockRAM-based), there is no possible way to map
> > such a HDL description to the FPGA device.

>
> Thanks for your answer Nathan, so I cant have a register file that has 4
> read ports and 2 write ports with a Virtex II? Well, unfortunately I
> need these number of ports else my ISA is not working. Perhaps do you
> know any FPGA boards that support Register Files which would allow such
> a design as I have it? Would be very thankful for feedback!
>
> Cheers
> Andrew


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  #9 (permalink)  
Old 11-15-2007, 12:50 AM
Nathan Bialke
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Default Re: Xilinx Virtex-II Newbie

However, to be slightly more helpful, you still can "fake it." Xilinx
suggests such a mechanism here: http://www.xilinx.com/support/docume...es/xapp228.pdf

Again, it comes down to creatively multiplexing ports.

- Nathan

On Nov 14, 2:49 pm, Andrew Ganger <[email protected]> wrote:
> > What you are asking for is outside the abilities of the Virtex-II
> > FPGA. Since the FPGA only contains dual-ported memories (either
> > SelectRAM-based or BlockRAM-based), there is no possible way to map
> > such a HDL description to the FPGA device.

>
> Thanks for your answer Nathan, so I cant have a register file that has 4
> read ports and 2 write ports with a Virtex II? Well, unfortunately I
> need these number of ports else my ISA is not working. Perhaps do you
> know any FPGA boards that support Register Files which would allow such
> a design as I have it? Would be very thankful for feedback!
>
> Cheers
> Andrew


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  #10 (permalink)  
Old 11-15-2007, 01:34 AM
Peter Alfke
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Default Re: Xilinx Virtex-II Newbie

On Nov 14, 2:49 pm, Andrew Ganger <[email protected]> wrote:
Virtex-2 or any other Virtex FPGA can implement a RAM with any desired
number of ports, if you are willing to time-share operation and
multiplex addresses and data. So it is just a trade-off.
The BlockRAMs in all Virtex devices have two independent ports, so you
can perform two independent accesses simultaneously (two writes, two
reads, or a mixture of write and read). Further ports can be created
by time-sharing and multiplexing, which of course costs chip area and
increases access time. But those are the usual trade-offs that smart
engineers are asked to evaluate and implement every day. What else is
new?
Peter Alfke, Xilinx

> > What you are asking for is outside the abilities of the Virtex-II
> > FPGA. Since the FPGA only contains dual-ported memories (either
> > SelectRAM-based or BlockRAM-based), there is no possible way to map
> > such a HDL description to the FPGA device.

>
> Thanks for your answer Nathan, so I cant have a register file that has 4
> read ports and 2 write ports with a Virtex II? Well, unfortunately I
> need these number of ports else my ISA is not working. Perhaps do you
> know any FPGA boards that support Register Files which would allow such
> a design as I have it? Would be very thankful for feedback!
>
> Cheers
> Andrew


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  #11 (permalink)  
Old 11-15-2007, 01:37 AM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> My question should be: do you have instructions that use 4 register
> operands?


Yes, I have defined an own ISA. There are instructions that take up to
4 src operands and can write up to two results back to the register
file. So I need these 4 read ports for some, not all, instructions!
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  #12 (permalink)  
Old 11-15-2007, 01:40 AM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> What CPU are you using ?


Well, in some way I have defined my own ISA. The instructions can take
up to 4 src registers and can produce 2 results. Else it is a classical
5 stage pipeline with 16 registers in the register file.
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  #13 (permalink)  
Old 11-15-2007, 01:54 AM
Jim Granville
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Default Re: Xilinx Virtex-II Newbie

Andrew Ganger wrote:
> Andrew Ganger wrote:
>
>> UNfortuantely I just have version 7.1 and I should have a RAM that has
>> 4 read ports and 2 write ports? Is that somehow to realise with ISE
>> 7.1 or do I need to upgrade to version 8.1?

>
>
> Mixed something up, my Register File should have 4 read ports and two
> write ports


Two write ports sounds dangerous - but classic RISC devices
might need 3 read ports, and one write port

Rd = Ra OPERAND Rb OPERAND Rc

one fast/simple idea I had for emulating this on dualport memory is to
use two blocks and simply parallel the one write port
- so the two have identical info, and would actually give 4 read ports

Yes, it's a little redundant, but easy to implement, and the RegFiles
are small anyway.

-jg

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  #14 (permalink)  
Old 11-15-2007, 02:12 AM
EEngineer
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Default Re: Xilinx Virtex-II Newbie

On Nov 14, 5:55 pm, Andrew Ganger <[email protected]> wrote:
> > Are you sure that you need 4 read and 2 write ports? Do you need to
> > assign the data read at the time - at the same clock edge? In that
> > case you could just assign the same data read to multiple signals.

>
> > How big is your register file?

>
> Thanks for your answer Dan, I need a data and instruction RAM with one
> read/write port each but I would need a register file with 4 read ports
> and 2 write ports. Is such a thing feasable with Virtex II? If not, are
> there any FPGA Boards that would support 4 Read Ports and 2 Write Ports
> Register Files? The register File itself contains 16 registers, each of
> 32bits.And in the worst case it can happen that at the same clock cycle
> I have to read 4 registers and to write back 2 values.
>
> Cheers,
> Andrew


Are you implementing MIPS32? Do you have instructions that have two
register operands?
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  #15 (permalink)  
Old 11-15-2007, 02:15 AM
EEngineer
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Default Re: Xilinx Virtex-II Newbie

On Nov 14, 9:12 pm, EEngineer <[email protected]> wrote:
> On Nov 14, 5:55 pm, Andrew Ganger <[email protected]> wrote:
>
>
>
> > > Are you sure that you need 4 read and 2 write ports? Do you need to
> > > assign the data read at the time - at the same clock edge? In that
> > > case you could just assign the same data read to multiple signals.

>
> > > How big is your register file?

>
> > Thanks for your answer Dan, I need a data and instruction RAM with one
> > read/write port each but I would need a register file with 4 read ports
> > and 2 write ports. Is such a thing feasable with Virtex II? If not, are
> > there any FPGA Boards that would support 4 Read Ports and 2 Write Ports
> > Register Files? The register File itself contains 16 registers, each of
> > 32bits.And in the worst case it can happen that at the same clock cycle
> > I have to read 4 registers and to write back 2 values.

>
> > Cheers,
> > Andrew

>
> Are you implementing MIPS32? Do you have instructions that have two
> register operands?


My question should be: do you have instructions that use 4 register
operands?
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  #16 (permalink)  
Old 11-15-2007, 02:37 AM
Jim Granville
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Default Re: Xilinx Virtex-II Newbie

Andrew Ganger wrote:
>
>> Are you sure that you need 4 read and 2 write ports? Do you need to
>> assign the data read at the time - at the same clock edge? In that
>> case you could just assign the same data read to multiple signals.
>>
>> How big is your register file?

>
>
> Thanks for your answer Dan, I need a data and instruction RAM with one
> read/write port each but I would need a register file with 4 read ports
> and 2 write ports. Is such a thing feasable with Virtex II? If not, are
> there any FPGA Boards that would support 4 Read Ports and 2 Write Ports
> Register Files? The register File itself contains 16 registers, each of
> 32bits.And in the worst case it can happen that at the same clock cycle
> I have to read 4 registers and to write back 2 values.


What I described in my other post can do this too. (it would be up to
the user to make sure the writes did not collide ..)
Take 2 dual port memories, and parallel the write ports, on each side,
but separate the read ports. As you always write before read, the info
in the two is always identical. With a FPGA, done this way, you can
also add 1 cycle register bank-switching for interrupts, or a register
page scheme, to use larger dual-port memory.

What CPU are you using ?

-jg

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  #17 (permalink)  
Old 11-15-2007, 03:38 AM
Jim Granville
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Default Re: Xilinx Virtex-II Newbie

Andrew Ganger wrote:
>
>> My question should be: do you have instructions that use 4 register
>> operands?

>
>
> Yes, I have defined an own ISA. There are instructions that take up to
> 4 src operands and can write up to two results back to the register
> file. So I need these 4 read ports for some, not all, instructions!


So that's 24 bits of operand, leaves 8 bits of opcode, if 32 bit ?

Which opcodes need to write two results, in one cycle ?

I can think of MUL, DIV, MOD that might write two results,
(but not so much in one cycle)
but the only other instances I could think of would be
extended size opcodes (normally handled reg-paired), and maybe
merge of a MOV.

Source code does not tend to have two writes per expression ?

-jg

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  #18 (permalink)  
Old 11-15-2007, 04:03 AM
Joseph H Allen
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Default Re: Xilinx Virtex-II Newbie

In article <[email protected]>,
Andrew Ganger <[email protected]> wrote:

>my Register File should have 4 read ports and two
>write ports


You have several options besides time multiplexing the existing RAM:

- Implement the RAM using flops instead of RAM. This may be reasonable if
you do not have too many registers. I'm not sure if xst will infer the
flops, but I would try something like this:

reg [31:0] r[15:0]; // 512 flops, not ram.

always @(posedge clk)
begin
if (write_enable_a) r[write_addr_a] <= write_data_a;
if (write_enable_b) r[write_addr_b] <= write_data_b;
end

- Use XOR differences. Each write port writes to a set of RAMs- you want
two ports, so there will be set A and set B. Each set of RAMs is made up
of a bunch of dual-port async read RAMs (Xilinx distributed RAM) in
parallel. Within each set, the write side of these dual port RAMs are all
tied together and use a single address. The read ports all get their own
addresses.

So this is how it works: each read port is created by XORing a read port
from set A and one from set B. So lets say write port A wants to write an
X to location N- it has to write A'[N] <= X ^ B[N] so that on read you will
have X == (A'[N]) ^ B[N] == (X ^ B[N]) ^ B[N] == X.

This means that each set needs a read port for the writer of the other
set, plus a read port for each final read port. For two write ports and
four read ports you will need 5 ports in each set: 10 dual-port
distributed RAMs total per bit.

To simulate a superscalor or VLIW CPU you need many read ports and many
write ports, so any way you do it gets to be very expensive.

--
/* [email protected] AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
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  #19 (permalink)  
Old 11-15-2007, 01:15 PM
Andreas Ehliar
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Default Re: Xilinx Virtex-II Newbie

On 2007-11-14, Andrew Ganger <[email protected]> wrote:
> I am just reading the XST userguide. There it says that with version
> 8.1i it is possible to directly specify data with the RAM module or
> load it from an external source. IN addition it says the multiple write
> ports in the RAM are supported from version 8.1 on. UNfortuantely I just
> have version 7.1 and I should have a RAM that has 4 read ports and 2
> write ports? Is that somehow to realise with ISE 7.1 or do I need to
> upgrade to version 8.1?


Hi, as others have pointed out you can create a register file with
one write port and several read ports quite efficient. Could you constrain
your instruction set so that the instruction that need to write to two
registers is limited to a register pair of even and odd registers?

As in: (R1,R0) = R2*R3 ; Ok R1 odd, R0 even
And: (R2,R0) = R4*R5 ; Not OK, Both R2 and R0 are even

In that case you can implement your register file as two memories with
one write port.

/Andreas
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  #20 (permalink)  
Old 11-15-2007, 02:27 PM
Brian Drummond
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Default Re: Xilinx Virtex-II Newbie

On Wed, 14 Nov 2007 23:49:25 +0100, Andrew Ganger
<[email protected]> wrote:

>
>> What you are asking for is outside the abilities of the Virtex-II
>> FPGA. Since the FPGA only contains dual-ported memories (either
>> SelectRAM-based or BlockRAM-based), there is no possible way to map
>> such a HDL description to the FPGA device.

>
>Thanks for your answer Nathan, so I cant have a register file that has 4
>read ports and 2 write ports with a Virtex II? Well, unfortunately I
>need these number of ports else my ISA is not working.


Register file should be no problem, inplemented in the FPGA fabric;
though it could be fairly large (assuming your description is
synthesisable). I suspect Nathan was talking about multi-port larger
blocks of memory.

Even there you can do it; multiplexing is simplest if your performance
needs are low, but it's not the only way. For example, to increase the
number of read ports, you can simply parallel memories, writing to them
all simultaneously. If you can get away with 2:1 multiplexing the write
ports, that may be all you need.

Do you need full bandwidth on all six ports simultaneously?

In any case, use the component you have as a wrapper for the detailed
implementation for that behaviour.

- Brian

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  #21 (permalink)  
Old 11-15-2007, 02:38 PM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> I can think of MUL, DIV, MOD that might write two results,
> (but not so much in one cycle)
> but the only other instances I could think of would be
> extended size opcodes (normally handled reg-paired), and maybe
> merge of a MOV.
>
> Source code does not tend to have two writes per expression ?


Yeah, multiplication is one example that uses two write ports.
The ISA is tailored towards a very specific domain of applications,
so therefore I have some not straight forward instructions. But
it would be handy in this case to have instructions that take 4 inputs
and generate 2 outputs.
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  #22 (permalink)  
Old 11-15-2007, 02:41 PM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> Two write ports sounds dangerous - but classic RISC devices
> might need 3 read ports, and one write port
>
> Rd = Ra OPERAND Rb OPERAND Rc
>
> one fast/simple idea I had for emulating this on dualport memory is to
> use two blocks and simply parallel the one write port
> - so the two have identical info, and would actually give 4 read ports
>
> Yes, it's a little redundant, but easy to implement, and the RegFiles
> are small anyway.


Yeah, it might be dangerous, but in my case I would need two write ports .

So yeah, this sounds like a good idea. So I would have two RAM blocks
each with two read, and two write ports. In this case I write the result
back simultanlously in both register files. Looks like a good idea for
a first evaluation!

Thanks!
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  #23 (permalink)  
Old 11-15-2007, 02:47 PM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> Register file should be no problem, inplemented in the FPGA fabric;
> though it could be fairly large (assuming your description is
> synthesisable). I suspect Nathan was talking about multi-port larger
> blocks of memory.


Thanks for your comment Brian. I will try and see what the tool tells me
when trying to synthesise it. Is there an upper limit for read and write
ports for such kind of register files? Or is this just the case for
memories?

> Even there you can do it; multiplexing is simplest if your performance
> needs are low, but it's not the only way. For example, to increase the
> number of read ports, you can simply parallel memories, writing to them
> all simultaneously. If you can get away with 2:1 multiplexing the write
> ports, that may be all you need.


Yeah that also sounds like a good idea. But as memory I have a simple
single port read/write interface!

Cheers!

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  #24 (permalink)  
Old 11-15-2007, 03:12 PM
EEngineer
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Posts: n/a
Default Re: Xilinx Virtex-II Newbie

On Nov 15, 9:41 am, Andrew Ganger <[email protected]> wrote:
> > Two write ports sounds dangerous - but classic RISC devices
> > might need 3 read ports, and one write port

>
> > Rd = Ra OPERAND Rb OPERAND Rc

>
> > one fast/simple idea I had for emulating this on dualport memory is to
> > use two blocks and simply parallel the one write port
> > - so the two have identical info, and would actually give 4 read ports

>
> > Yes, it's a little redundant, but easy to implement, and the RegFiles
> > are small anyway.

>
> Yeah, it might be dangerous, but in my case I would need two write ports .
>
> So yeah, this sounds like a good idea. So I would have two RAM blocks
> each with two read, and two write ports. In this case I write the result
> back simultanlously in both register files. Looks like a good idea for
> a first evaluation!
>
> Thanks!


Probelem with this is what if more than two registers that need to be
written are located at the same RAM block! I am using 8 parallel
blocks in my design as I am writting 8 memory locations at a time but
I am sure that all 8 memory locations belong to different RAM block.
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  #25 (permalink)  
Old 11-15-2007, 03:44 PM
Andrew Ganger
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Default Re: Xilinx Virtex-II Newbie


> Hi, as others have pointed out you can create a register file with
> one write port and several read ports quite efficient. Could you constrain
> your instruction set so that the instruction that need to write to two
> registers is limited to a register pair of even and odd registers?
>
> As in: (R1,R0) = R2*R3 ; Ok R1 odd, R0 even
> And: (R2,R0) = R4*R5 ; Not OK, Both R2 and R0 are even
>
> In that case you can implement your register file as two memories with
> one write port.


Sorry, I dont understand that. You suggest also to use 2 RAM block with
each two read ports. They both should contain the same register values,
so in other words, each RAM block requires 2 write ports so that I can
keep the values in both registers consistent!
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