FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-01-2007, 11:48 PM
Guest
 
Posts: n/a
Default To Xilinx users - PLB bus features (for PPC)

Hi,
It is mentioned in xilinx data sheets that the the CoreConnect PLB bus
has lots of great capabilities (e.g. address pipelineing , bursts
etc.).
I wonder how can I (as a user) can bring the PPC to use these
capabilities, saying how can I force a burst write or read ? or how
can I start a write while a read is in progress ?
Is there a special SW command/syntax that make the PPC PLB Date side
master to write a burst or does it do it automatically ?
I will be greatfull for any help on this..
Thanks, Mordeahy.

Reply With Quote
  #2 (permalink)  
Old 11-02-2007, 04:55 AM
Guest
 
Posts: n/a
Default Re: To Xilinx users - PLB bus features (for PPC)

On Nov 1, 5:48 pm, [email protected] wrote:
> Hi,
> It is mentioned in xilinx data sheets that the the CoreConnect PLB bus
> has lots of great capabilities (e.g. address pipelineing , bursts
> etc.).
> I wonder how can I (as a user) can bring the PPC to use these
> capabilities, saying how can I force a burst write or read ? or how
> can I start a write while a read is in progress ?
> Is there a special SW command/syntax that make the PPC PLB Date side
> master to write a burst or does it do it automatically ?
> I will be greatfull for any help on this..
> Thanks, Mordeahy.



The PowerPC will do single beat transactions (8 bit,16 bit, and 32
bit) and cache line transactions. If it is addressing memory that has
been mapped as cacheable, it will automatically do a cache line
transaction.The default is to do 32 byte cache lines, but you can set
it to do two other sizes as well via one of the special machine state
registers. I think that it is 16 and 64 bytes, but I would have to
double check that. The PPC does not do any of the other burst
transaction.

The data and instruction caches each have their own master PLB
interface, so one of them can be doing a read while the other is doing
a write. I do not believe that an individual PPC PLB interfaces will
do simultaneous reads and writes, but I would have to look at the
Xilinx PPC users guide to verify that.

The PLB bus will indeed support these modes. We have a PLB to DDR2
interface, and a PLB master interface that support simultaneous reads
and writes for the single beat, burst and cache transactions, and it
is a thing of beauty to watch that in action.

Regards,

John McCaskill
www.fastertechnology.com

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
ddr with multiple users David Ashley FPGA 27 09-14-2006 05:30 PM
Any *really old* Viewlogic / Xilinx users around here? :) Peter FPGA 2 07-14-2006 02:52 AM
Question for the EDK ppc users ... [email protected] FPGA 4 03-07-2006 05:52 AM
Xilinx EDK : mb-gcc linker errors with C++ features Guru FPGA 0 10-13-2005 06:01 PM
Features of Xilinx ISE WebPACK & Altera's Quartus II. Antti Karttunen (remove the trailing .do from the address) FPGA 2 10-06-2004 02:25 AM


All times are GMT +1. The time now is 06:49 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved