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  #1 (permalink)  
Old 11-23-2007, 09:08 AM
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Default xilinx spartan 3 + 16 adc

Hi

I'd like to ask if that device will process data from 16 ADC (20 bit,
44,1kHz) to one output stream (does it depend on ADC clock - i mean
adc input clock = amount of output samples/s ? ) ? Or maybe i should
consider using external input buffers ?

thx in advance
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  #2 (permalink)  
Old 11-23-2007, 09:40 AM
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Default Re: xilinx spartan 3 + 16 adc

On 23 Lis, 10:08, [email protected] wrote:
> Hi
>
> I'd like to ask if that device will process data from 16 ADC (20 bit,
> 44,1kHz) to one output stream (does it depend on ADC clock - i mean
> adc input clock = amount of output samples/s ? ) ? Or maybe i should
> consider using external input buffers ?


Could you be more specific?
What kind of ADC?
What kind of spartan3?
What exactly do you want to do?

Regards,

Jerzy Gbur
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  #3 (permalink)  
Old 11-23-2007, 12:31 PM
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Default Re: xilinx spartan 3 + 16 adc


sorry i did miss "xc3s50"
i want to connect 16 outputs from ADC (dont know specification yet) to
FPGA inputs and convert them to one stream.

regards

On 23 Lis, 10:40, "[email protected]" <[email protected]> wrote:
> On 23 Lis, 10:08, [email protected] wrote:
>
> > Hi

>
> > I'd like to ask if that device will process data from 16 ADC (20 bit,
> > 44,1kHz) to one output stream (does it depend on ADC clock - i mean
> > adc input clock = amount of output samples/s ? ) ? Or maybe i should
> > consider using external input buffers ?

>
> Could you be more specific?
> What kind of ADC?
> What kind of spartan3?
> What exactly do you want to do?
>
> Regards,
>
> Jerzy Gbur


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  #4 (permalink)  
Old 11-23-2007, 12:52 PM
taco
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Default Re: xilinx spartan 3 + 16 adc

[email protected] wrote:

>
> sorry i did miss "xc3s50"
> i want to connect 16 outputs from ADC (dont know specification yet) to
> FPGA inputs and convert them to one stream.
>
> regards
>

the 44.1 khz is a serial output rate of the ADC? and the total output rate
without headers, dataprocessing or whatever is 44.1*20*16= 14 Mbps? Should
be possible with such a device if you choose a correct clock frequency.
Taco


> On 23 Lis, 10:40, "[email protected]" <[email protected]> wrote:
>> On 23 Lis, 10:08, [email protected] wrote:
>>
>> > Hi

>>
>> > I'd like to ask if that device will process data from 16 ADC (20 bit,
>> > 44,1kHz) to one output stream (does it depend on ADC clock - i mean
>> > adc input clock = amount of output samples/s ? ) ? Or maybe i should
>> > consider using external input buffers ?

>>
>> Could you be more specific?
>> What kind of ADC?
>> What kind of spartan3?
>> What exactly do you want to do?
>>
>> Regards,
>>
>> Jerzy Gbur


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  #5 (permalink)  
Old 11-26-2007, 08:40 PM
MM
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Default Re: xilinx spartan 3 + 16 adc

"taco" <[email protected]> wrote in message
news:[email protected]
> [email protected] wrote:
>
> the 44.1 khz is a serial output rate of the ADC? and the total output rate
> without headers, dataprocessing or whatever is 44.1*20*16= 14 Mbps?
> Should
> be possible with such a device if you choose a correct clock frequency.
> Taco


I am sure the OP is talking about audio ADCs, so 44.1 kHz is not serial rate
but rather parallel. However, your calculation of the total bandwidth
required is still correct... Obviously this speed is not an issue with any
of the modern FPGAs.



/Mikhail


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  #6 (permalink)  
Old 11-26-2007, 09:33 PM
Peter Alfke
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Default Re: xilinx spartan 3 + 16 adc

The issue will be the number of parallel inputs to the FPGA.
16 x 20 bits would require 320 data inputs, unless you can do some
external multiplexing or data ORing..
Once inside the FPGA, the bandwidth should be no problem.
Peter Alfke, Xilinx Applications

On Nov 26, 12:40 pm, "MM" <[email protected]> wrote:
> "taco" <[email protected]> wrote in message
>
> news:[email protected]
>
> > [email protected] wrote:

>
> > the 44.1 khz is a serial output rate of the ADC? and the total output rate
> > without headers, dataprocessing or whatever is 44.1*20*16= 14 Mbps?
> > Should
> > be possible with such a device if you choose a correct clock frequency.
> > Taco

>
> I am sure the OP is talking about audio ADCs, so 44.1 kHz is not serial rate
> but rather parallel. However, your calculation of the total bandwidth
> required is still correct... Obviously this speed is not an issue with any
> of the modern FPGAs.
>
> /Mikhail


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  #7 (permalink)  
Old 11-26-2007, 11:22 PM
Jim Granville
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Default Re: xilinx spartan 3 + 16 adc

Peter Alfke wrote:
> The issue will be the number of parallel inputs to the FPGA.
> 16 x 20 bits would require 320 data inputs, unless you can do some
> external multiplexing or data ORing..
> Once inside the FPGA, the bandwidth should be no problem.


?
I'm not sure I have ever seen a 20+ bit 44Khz samplig ADC with a
parallel data stream ?
Most use a SSI serial interface (which is where the 14 Mbps numbers
are coming from )
So, depending on what the OP means exactly by "process data",
this looks doable in a FPGA.

-jg

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  #8 (permalink)  
Old 11-27-2007, 02:12 PM
Brian Drummond
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Default Re: xilinx spartan 3 + 16 adc

On Tue, 27 Nov 2007 12:22:00 +1300, Jim Granville
<[email protected]> wrote:

>Peter Alfke wrote:
>> The issue will be the number of parallel inputs to the FPGA.
>> 16 x 20 bits would require 320 data inputs, unless you can do some
>> external multiplexing or data ORing..
>> Once inside the FPGA, the bandwidth should be no problem.

>
>?
>I'm not sure I have ever seen a 20+ bit 44Khz samplig ADC with a
>parallel data stream ?


Can't recall any offhand. It was common enough in the 16 bit days
though. There may have been 20-bit offerings from some of the hybrid
manufacturers, Analogic maybe?

- Brian

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  #9 (permalink)  
Old 11-27-2007, 03:27 PM
MM
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Default Re: xilinx spartan 3 + 16 adc

"Jim Granville" <[email protected]> wrote in message
news:[email protected]
>
> I'm not sure I have ever seen a 20+ bit 44Khz samplig ADC with a parallel
> data stream ?
> Most use a SSI serial interface (which is where the 14 Mbps numbers
> are coming from )


Sure the output of the ADC is most likely serial. I was just trying to say
that the 44.1 kHz is not the data output serial clock, but rather the output
sampling clock frequency.

/Mikhail


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