FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 06-23-2008, 03:12 PM
XSterna
Guest
 
Posts: n/a
Default Xilinx and RAM/ROM monitoring

Hi,

I was wondering if a tool exists to monitor the content of a RAM, ROM
connected to a Xilinx FPGA.

I would like to be able to control the content of those memories like
a debugging tool for microcontroller for example.

Does anybody know if this type of "debug" option is available for FPGA
developpment ?

Xavier
Reply With Quote
  #2 (permalink)  
Old 06-27-2008, 06:26 PM
Gabor
Guest
 
Posts: n/a
Default Re: Xilinx and RAM/ROM monitoring

On Jun 23, 10:12 am, XSterna <[email protected]> wrote:
> Hi,
>
> I was wondering if a tool exists to monitor the content of a RAM, ROM
> connected to a Xilinx FPGA.
>
> I would like to be able to control the content of those memories like
> a debugging tool for microcontroller for example.
>
> Does anybody know if this type of "debug" option is available for FPGA
> developpment ?
>
> Xavier


Xilinx Platform Studio SDK allows you to monitor and change any memory
accessible by the embedded processor in your system. I have done this
with MicroBlaze on Virtex 5, but I assume it works on the PPC
processors
as well. I don't know of a general tool for attached memory that is
not associated with an embedded processor.

Regards,
Gabor
Reply With Quote
Reply

Bookmarks


Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
PPC405 Performance Monitoring Anthony Mahar FPGA 9 04-15-2005 05:48 AM
Altera Avalon Bus Signal Monitoring? Pino FPGA 0 07-19-2004 03:35 AM


All times are GMT +1. The time now is 11:56 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2024, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved