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Old 04-27-2006, 04:08 PM
Dolphin
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Default Xilinx: Prohibit propagation of timing constraint through a mux


Hello,

Im my design I have an asynchr mux with two inputs and one output:
- In1
- In2
- Out

I have FFS on In1 clock, on In2 clock and on the Out clock.
If the mux selects In1 clock then there is a datapath from the FFS(In
domain) to the FFS(Out) domain.
If the mux selects In2 clock then there is a datapath from the FFS(In
domain) to the FFS(Out) domain.

How should I constrain this?
Now I (try to) group the elements:
NET "In1" TNM_NET = FFS(*) "TNM_In1"; #60 MHz
NET "In2" TNM_NET = FFS(*) "TNM_In2"; #50 MHz
NET "Out" TNM_NET = FFS(*) "TNM_Out";
And I give a period constraint on these three clocks.
I also give a from to constraint for In1 => Out and for In2 => Out.
To be complete I constrain the length of the path from In1 to out and fro
In2 to out.
The problem is that the worst case timing constraint is propagated throug
the mux, as a consequence my TNM groups are not correct:
TNM_In1 = all FFS in the In1 and the out domain.
TNM_In2 = all FFS in the In2 domain
TNM_Out = empty
My from-to constraints don't work because my tnm groups are not correct.

Has anyone had a similar problem?

best regards,
Karel D

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Old 04-27-2006, 04:20 PM
Peter Alfke
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Default Re: Xilinx: Prohibit propagation of timing constraint through a mux

Using a mux to select between two different clocks can cause you a lot
of trouble, because you must avoid output glitches.
I published an absolutely safe solution as the final item in "Six eeasy
pieces" as TechXclusives (search for it on the Xilinx website.)
That design is guaranteed to switch glitchfree between two free-running
clocks, no matter when or how you activate the Select input.
Peter Alfke, Xilinx Applications

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Old 04-28-2006, 04:50 AM
Jeff Brower
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Default Re: Xilinx: Prohibit propagation of timing constraint through a mux

Karel-

I have fought with this also. My conclusion is that clock-oriented
timing constraints, including CLOCK_SIGNAL constraint, are basically
worthless for fabric signals. If there is any app note that truly
shows how to use them on non-clock signals, I'd sure like to see it.
Once you cause XST to "jump off the clock net" as Austin puts it, I
don't know what you do to get back on it.

If your clocks are truly free-running, and you never have to switch
away from a dead clock, then simply use a BUFGMUX, as has been
suggested many times on the group. You will be good.

If one clock is free-running, but one may stop, then you might still be
able to use a BUFGMUX by doing this:

-Use I0 input on the BUFGMUX for the always-running clock

-ensure the clock that could stop (on I1 input) always stops at a
low-level

-use a state-machine based on another, independent clock to measure
the output of the BUFGMUX and determine when to switch

Following these guidelines, a BUFGMUX appears to work without getting
stuck. There may be some Xilinx evidence to support this, if you look
carefully at behavior of a BUFGCE, which is a BUFGMUX with I1 tied to
GND and sel line used as CE (enable). With a BUFGCE, the CE line can
be toggled any time. I am in the process of testing the above use of a
BUFGMUX billions of times to verify.

I would like to take this opportunity to ask that Peter and Austin to
let us know exactly what is the circuitry in the BUFGMUX. It's too
important a feature to be guessing how it behaves when its inputs are
not always running. If it does not exactly match Peter's Six Easy
Pieces circuit, which I suspect it does not based on what I've heard on
this group, then we should know the modifications. If this info is
covered under NDA that should be Ok as people who need to know should
have no trouble to go that route.

-Jeff

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Old 04-28-2006, 07:31 AM
Dolphin
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Default Re: Xilinx: Prohibit propagation of timing constraint through a mux

>Using a mux to select between two different clocks can cause you a lot
>of trouble, because you must avoid output glitches.
>I published an absolutely safe solution as the final item in "Six eeasy
>pieces" as TechXclusives (search for it on the Xilinx website.)
>That design is guaranteed to switch glitchfree between two free-running
>clocks, no matter when or how you activate the Select input.
>Peter Alfke, Xilinx Applications
>
>


Hello Peter,

I think I shouldn't care about the glitches: the datapath is in reset whe
a clock switching occurs. The reset is deactivated once the switch ha
changed state.
My biggest problem are the constraints; how should I constrain th
datapath in the three different clock domains?

Thanks and best regards,
Karel Deprez

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  #5 (permalink)  
Old 04-28-2006, 04:52 PM
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Default Re: Xilinx: Prohibit propagation of timing constraint through a mux

You can try to play with the PRIORITY keyword: e.g.

# the lower the PRIORITY number, the higher the priority
TIMESPEC TS_In1 = PERIOD In1 60 MHz PRIORITY 0;
TIMESPEC TS_In2 = PERIOD In2 50 MHz PRIORITY 1;

HTH,
Jim
(jimwu88 at yahoo dot com)

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