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Old 05-31-2009, 01:37 AM
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Default Xilinx PDR flow questions - Time function and DDR RAM access

Hello, just some questions concerning the EAPR flow for Xilinx..

The examples related to the EAPR allow to access the bitstreams stored
in a compact flash (SystemACE) .. Has any body any experience in
moving the bitstreams to a DDR RAM initially and let the ICAP access
the bitstreams from there .. ? What are the advantages and
disadvantages ..

Also i would like to know if there are any C functions that i can add
to the processor code to print out the reconfiguration time between
the switching of the bitstreams ?

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