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Old 11-04-2007, 02:03 PM
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Default Xilinx PCI-Express Endpoint Block IP

There is only 8 bit interface wrapper(pcie_gt_wrapper.v) from Xilinx
PCI-Express Endpoint Block IP. it means that it needs 250MHz clk.In
general,it is impossible to achieve 250Mhz clk with large
design.So,we
need 16bit interface wrapper so that the clk can be reduced 125Mhz.
it
is very easy to implement.is there avaliable 16bit wrapper?

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Old 11-04-2007, 08:45 PM
sovan
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Default Re: Xilinx PCI-Express Endpoint Block IP

I think it should be possible to design a 16-bit interface wrapper
around the GTP. Buf if you are using the PCIE_EP hard block then the
Transceiver interface is 8-bit PIPE interface. So we don't gain much
by having a 16-bit interface wrapper for GTP.

In my design I have registers in all the connections between PCIE_EP
and GTP. It works fine for x1 and x4. There wasn't any timing issue.
My core_clock is 250 MHz and user_clock is 125 MHz.

-Sovan.

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Old 11-05-2007, 01:34 AM
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Default Re: Xilinx PCI-Express Endpoint Block IP

On 11 5 , 4 45 , sovan <[email protected]> wrote:
> I think it should be possible to design a 16-bit interface wrapper
> around the GTP. Buf if you are using the PCIE_EP hard block then the
> Transceiver interface is 8-bit PIPE interface. So we don't gain much
> by having a 16-bit interface wrapper for GTP.
>
> In my design I have registers in all the connections between PCIE_EP
> and GTP. It works fine for x1 and x4. There wasn't any timing issue.
> My core_clock is 250 MHz and user_clock is 125 MHz.
>
> -Sovan.


I only need the PCIE GTP wrapper of Xilinx Endpoint Block,no Endpoint
Block hard core.I have customized my PCIE controller.it works well.

But i need a 16bit interface wrapper around the GTP.so,my user_clk can
be reduced 125MHz.

my steps is

1>generate a standard 16bit PCIE wrapper with Xilinx Coregen wizard1.7

2>overwritte the all 16bit file tile header parameters with 8bit PCIE
Endpoint Block parameter

any other modified?


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