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  #1 (permalink)  
Old 04-27-2006, 11:40 AM
sjulhes
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Default Xilinx PCI 64/32 bits IP

Hello,

We have a design with master PCI DMA in 64 bits. This design implements the
xilinx PCI 64/32 bits IP.
The problem is that our board should be plugged in various versions of the
PCI bus ( 64 bits/ 66 Mhz and 32 bits/ 33 mhz, 32 bits / 66 Mhz ).

My question is : Is the IP abble to transparently handle the fact that the
board is plugged in a 32 or 64 bit PCI slot ?

The goal is to have only one design that feeds the PCI master DMA section
with 64 bits data whether the bus is 32 or 64 bits wide.

What are the limitations with this IP ?
Are there specifics configuration or design stuffs to add ?

Thanks for your feedbacks.

Stéphane.




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  #2 (permalink)  
Old 04-27-2006, 05:34 PM
John_H
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Default Re: Xilinx PCI 64/32 bits IP

Read the Logicore PCI v3.0 User Guide, Initiator 64-bit Extension,
Additional Considerations, Monitor the Target Response.

It appears the PCI spec requires that the user handle the switch from a
desired 64-bit initiator transaction as a 32-bit sequence after the original
attempt at a 64-bit transaction is terminated by the target.


"sjulhes" <[email protected]> wrote in message
news:[email protected]
> Hello,
>
> We have a design with master PCI DMA in 64 bits. This design implements
> the
> xilinx PCI 64/32 bits IP.
> The problem is that our board should be plugged in various versions of the
> PCI bus ( 64 bits/ 66 Mhz and 32 bits/ 33 mhz, 32 bits / 66 Mhz ).
>
> My question is : Is the IP abble to transparently handle the fact that the
> board is plugged in a 32 or 64 bit PCI slot ?
>
> The goal is to have only one design that feeds the PCI master DMA section
> with 64 bits data whether the bus is 32 or 64 bits wide.
>
> What are the limitations with this IP ?
> Are there specifics configuration or design stuffs to add ?
>
> Thanks for your feedbacks.
>
> Stéphane.
>
>
>
>



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  #3 (permalink)  
Old 04-27-2006, 11:32 PM
Jeff Brower
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Default Re: Xilinx PCI 64/32 bits IP

Stéphane-

> My question is : Is the [Xilinx PCI core] able to transparently handle the fact that the
> board is plugged in a 32 or 64 bit PCI slot ?


Do you see see REQ64 and ACK64 or similar signals on the module
interface?

-Jeff

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  #4 (permalink)  
Old 04-28-2006, 06:49 AM
sjulhes
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Posts: n/a
Default Re: Xilinx PCI 64/32 bits IP

Yes, here is the PCI signal I have for the PCI interface section of the
design :

entity pcim_top is
port (-- PCI ports; do not modify names!
AD : inout std_logic_vector(63 downto 0);
CBE : inout std_logic_vector( 7 downto 0);
PAR : inout std_logic;
PAR64 : inout std_logic;
FRAME_N : inout std_logic;
REQ64_N : inout std_logic;
TRDY_N : inout std_logic;
IRDY_N : inout std_logic;
STOP_N : inout std_logic;
DEVSEL_N : inout std_logic;
ACK64_N : inout std_logic;
IDSEL : in std_logic;
INTR_A : out std_logic;
PERR_N : inout std_logic;
SERR_N : inout std_logic;
REQ_N : out std_logic;
GNT_N : in std_logic;
RST_N : in std_logic;
PCLK : in std_logic;

As I'm just getting to PCI for this design, can someone quickly resume what
this process ( 64 bits design on a 64/32 bits interface ) is about ? What is
involved, what has to be added, what has to be watched compared to a
"normal" 64 bits design ( which I have ).

Thanks for your help !

Stéphane.


"Jeff Brower" <[email protected]> a écrit dans le message de news:
[email protected] com...
Stéphane-

> My question is : Is the [Xilinx PCI core] able to transparently handle the

fact that the
> board is plugged in a 32 or 64 bit PCI slot ?


Do you see see REQ64 and ACK64 or similar signals on the module
interface?

-Jeff



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  #5 (permalink)  
Old 04-28-2006, 07:32 AM
sjulhes
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Posts: n/a
Default Re: Xilinx PCI 64/32 bits IP

Thanks for the information.
I've just looked in the user manual to the sections you mention and it
explaines how my problem should be handled.
It is to the used to handle this using the M_FAIL64 signal.
I looked to the actual design I have to modifiy and it seems to be handled.

So I guess I have the answer to my question :
NO, the Xilinx IP doesn't handle it transparently, it is of the user's
responsability
YES, the actual design I have handles it

Thanks for your help.

Stéphane.

"John_H" <[email protected]> a écrit dans le message de news:
[email protected]
> Read the Logicore PCI v3.0 User Guide, Initiator 64-bit Extension,
> Additional Considerations, Monitor the Target Response.
>
> It appears the PCI spec requires that the user handle the switch from a
> desired 64-bit initiator transaction as a 32-bit sequence after the

original
> attempt at a 64-bit transaction is terminated by the target.
>
>
> "sjulhes" <[email protected]> wrote in message
> news:[email protected]
> > Hello,
> >
> > We have a design with master PCI DMA in 64 bits. This design implements
> > the
> > xilinx PCI 64/32 bits IP.
> > The problem is that our board should be plugged in various versions of

the
> > PCI bus ( 64 bits/ 66 Mhz and 32 bits/ 33 mhz, 32 bits / 66 Mhz ).
> >
> > My question is : Is the IP abble to transparently handle the fact that

the
> > board is plugged in a 32 or 64 bit PCI slot ?
> >
> > The goal is to have only one design that feeds the PCI master DMA

section
> > with 64 bits data whether the bus is 32 or 64 bits wide.
> >
> > What are the limitations with this IP ?
> > Are there specifics configuration or design stuffs to add ?
> >
> > Thanks for your feedbacks.
> >
> > Stéphane.
> >
> >
> >
> >

>
>



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