FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-29-2007, 05:58 PM
Simon Heinzle
Guest
 
Posts: n/a
Default Xilinx, MIG, UCF: timing constraints for DDR2 DRAM

Hi FPGA Group!

I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM interface,
generated with the Xilinx Memory Interface Generator. The complete system
consists of a PCI interface, an I/O DMA buffer, a burst module bursting from
DMA buffer to the DDR2 DRAM interface.

What is the best way to define setup/hold times for the I/O pads (UCF)?
(the RAM interface consists of a bi-dir data bus DQ, some output signals
e.g. A and the DRAM clocks CK)
1. Using the OFFSET = OUT 5 ns AFTER "SYS_CLK_P"? Unfortunately, this does
only work using the Input Clock Pin, but it should probably better be in
reference to the DRAM clocks CK)
2. Using TIMESPEC "TS_DDR_OUT" = FROM FFS TO "DDR_OUT" 5 ns; ? Is probably
better, but I'm not exactly sure.

Furthermore, how would you tackle the problem if the timing at the pads
cannot be met?

Thanks in advance for helpful answers and pointers in the right direction!

Best regards,
Simon



Reply With Quote
  #2 (permalink)  
Old 10-30-2007, 12:28 AM
Eric Crabill
Guest
 
Posts: n/a
Default Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM

Hi Simon,

This document may be of assistance:
http://www.xilinx.com/bvdocs/appnotes/xapp458.pdf

Eric

"Simon Heinzle" <[email protected]> wrote in message
news:[email protected]
> Hi FPGA Group!
>
> I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM
> interface, generated with the Xilinx Memory Interface Generator. The
> complete system consists of a PCI interface, an I/O DMA buffer, a burst
> module bursting from DMA buffer to the DDR2 DRAM interface.
>
> What is the best way to define setup/hold times for the I/O pads (UCF)?
> (the RAM interface consists of a bi-dir data bus DQ, some output signals
> e.g. A and the DRAM clocks CK)
> 1. Using the OFFSET = OUT 5 ns AFTER "SYS_CLK_P"? Unfortunately, this does
> only work using the Input Clock Pin, but it should probably better be in
> reference to the DRAM clocks CK)
> 2. Using TIMESPEC "TS_DDR_OUT" = FROM FFS TO "DDR_OUT" 5 ns; ? Is probably
> better, but I'm not exactly sure.
>
> Furthermore, how would you tackle the problem if the timing at the pads
> cannot be met?
>
> Thanks in advance for helpful answers and pointers in the right direction!
>
> Best regards,
> Simon
>
>
>



Reply With Quote
  #3 (permalink)  
Old 10-30-2007, 02:41 PM
Simon Heinzle
Guest
 
Posts: n/a
Default Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM

Thanks Eric,

I checked the XApp458 and various XApp7** about Virtex 4 DDR2, as we are
using a Virtex 4 FX. I'm using the DDR2 controller from the Memory Interface
Generator.

The main problem are the output delays. Input delays seem to be calibrated
using tap delay lines. I had a working example with output delays between
4.4ns and 5.1ns (Data, Address, Control, DRAM clock). I extended that
example (but no changes to the DRAM interface), now the output delays range
between 4.4 ns (Data, Control, Dram Clock) and 8.9 ns (Address).

What is are the best constraints to define a tight window? (I'm now using
TIMESPEC ... = FROM FFS TO "OUT" 5.3 ns, which cannot be met)
What is a good strategy to meet those timing constraints?

Thanks in advance,
Simon

"Eric Crabill" <[email protected]> wrote in message
news:[email protected]
> Hi Simon,
>
> This document may be of assistance:
> http://www.xilinx.com/bvdocs/appnotes/xapp458.pdf
>
> Eric
>
> "Simon Heinzle" <[email protected]> wrote in message
> news:[email protected]
>> Hi FPGA Group!
>>
>> I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM
>> interface, generated with the Xilinx Memory Interface Generator. The
>> complete system consists of a PCI interface, an I/O DMA buffer, a burst
>> module bursting from DMA buffer to the DDR2 DRAM interface.
>>
>> What is the best way to define setup/hold times for the I/O pads (UCF)?
>> (the RAM interface consists of a bi-dir data bus DQ, some output signals
>> e.g. A and the DRAM clocks CK)
>> 1. Using the OFFSET = OUT 5 ns AFTER "SYS_CLK_P"? Unfortunately, this
>> does only work using the Input Clock Pin, but it should probably better
>> be in reference to the DRAM clocks CK)
>> 2. Using TIMESPEC "TS_DDR_OUT" = FROM FFS TO "DDR_OUT" 5 ns; ? Is
>> probably better, but I'm not exactly sure.
>>
>> Furthermore, how would you tackle the problem if the timing at the pads
>> cannot be met?
>>
>> Thanks in advance for helpful answers and pointers in the right
>> direction!
>>
>> Best regards,
>> Simon
>>
>>
>>

>
>



Reply With Quote
  #4 (permalink)  
Old 10-30-2007, 05:41 PM
Simon Heinzle
Guest
 
Posts: n/a
Default Re: Xilinx, MIG, UCF: timing constraints for DDR2 DRAM

Hi all,

I found the problem: the "Retiming" option in Synplify Pro caused the
address signals to be retimed and they could therefore not be packed into an
IOB flip flop. This caused a much higher delay than in the other output
signals.

Thanks for your help,
Simon

"Simon Heinzle" <[email protected]> wrote in message
news:[email protected]
> Hi FPGA Group!
>
> I'm struggling to get a fast speed (~ 200 MHz) for the DDR2 DRAM
> interface, generated with the Xilinx Memory Interface Generator. The
> complete system consists of a PCI interface, an I/O DMA buffer, a burst
> module bursting from DMA buffer to the DDR2 DRAM interface.
>
> What is the best way to define setup/hold times for the I/O pads (UCF)?
> (the RAM interface consists of a bi-dir data bus DQ, some output signals
> e.g. A and the DRAM clocks CK)
> 1. Using the OFFSET = OUT 5 ns AFTER "SYS_CLK_P"? Unfortunately, this does
> only work using the Input Clock Pin, but it should probably better be in
> reference to the DRAM clocks CK)
> 2. Using TIMESPEC "TS_DDR_OUT" = FROM FFS TO "DDR_OUT" 5 ns; ? Is probably
> better, but I'm not exactly sure.
>
> Furthermore, how would you tackle the problem if the timing at the pads
> cannot be met?
>
> Thanks in advance for helpful answers and pointers in the right direction!
>
> Best regards,
> Simon
>
>
>



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Xilinx timing constraints incorrect? [email protected] FPGA 12 10-17-2007 08:11 PM
Xilinx Timing Constraints and failures [email protected] FPGA 1 01-30-2007 04:02 PM
Xilinx DCM and Timing Constraints Brad Smallridge FPGA 6 10-08-2004 08:45 PM
Xilinx Timing Constraints Brad Smallridge FPGA 4 09-30-2004 11:31 PM


All times are GMT +1. The time now is 03:32 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved