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Old 04-25-2006, 08:46 PM
johnp
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Default Xilinx Map vs IOB tri-state with clock enable...

I'm using XST 8.1 SP3 with a Spartan3 design. I'm trying to
use both the output and tri-state flip-flops in the IOB, but the
Xilinx tools are fighting me.

If I code my logic as:

always @(posedge ifclk)
amb_data_enable <= ~wr_pending;

always @(posedge ifclk)
if (dclkp)
o_data <= bits128 ? next_odata : {next_odata[63:0],
64'b0};

I end up using both the output and tri-state enable flip-flops in all
128
of the IOBs. Great!

BUT... If I change the code to be:

always @(posedge ifclk)
if (dclkp) // <--------------------------- NOTE THE CLOCK ENABLE
amb_data_enable <= ~wr_pending;

always @(posedge ifclk)
if (dclkp)
o_data <= bits128 ? next_odata : {next_odata[63:0],
64'b0};

The Xilinx tools no longer pack the tri-state enable flip-flop
into the IOB.

Looking at the IOB structure in the data sheet, this looks like it
should be
a legal construct that should take advantage of the IOB resources.

Has anyone seen this before? Any suggestions? I hate to waste time
opening a Web Case with Xilinx - I seldom get any reasonable answer
from them.

John Providenza

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Old 04-25-2006, 09:42 PM
johnp
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Default Re: Xilinx Map vs IOB tri-state with clock enable...

Here's more info....

I re-coded to get rid of the clock enable thinking that would
trivially fix my problem:

reg data_on;
wire data_enable;
always @(posedge ifclk)
if (dclkp)
data_on <= wr_pending;

assign data_enable = dclkp ? wr_pending : data_on ;

always @(posedge ifclk)
amb_data_disable <= ~data_enable;


always @(posedge ifclk)
if (dclkp)
o_data <= bits128 ? next_odata : {next_odata[63:0],
64'b0};

assign amb_dat = amb_data_disable ? 128'bz : o_data;

The above version works fine. I end up using the data_out and
tri-state regs
in the IOB. BUT... if I remove the "~" from the assignment
to amb_data_disable, the Xilinx tools again fail to use the flip-flop
in the IOB
that controls the tri-state. SO....

always @(posedge ifclk)
amb_data_disable <= ~data_enable; // ALLOWS IOB 3state
register

always @(posedge ifclk)
amb_data_disable <= data_enable; // BREAKS IOB 3state reigster

Also - in ISE 8.1, bothg Synthesis and Map have options to control IOB
register packing. Changing the Synthesis option to YES seemed to make
things worse.

XILINX: isn't it time that you finally fix the IOB register inference?
How much
time do we designers have to waste on this stupid problem?

John Providenza

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