FPGA Central

Hi all,

In our design, we have a sensitive circuitry that we think may be affected
by the bulk of the circuit (mainly two state machines). In order to isolate
it in a section of the FPGA (Virtex-II Pro XC2VP30), we tried using the
RLOC and RLOC_ORIGIN attributes. We did manage to group the sensitive
circuitry, and move it all the way to the bottom-left corner of the chip.
However, when we do that, the rest of the CLBs also move with them.

Although we tried to use the RLOC attribute for the rest of the circuit,
they are somehow not recognized. The reason might be that the files are in
different hierarchy levels, and the Xilinx Floorplanner doesn't recognize
the U_SET.

How do you suggest we go about doing this isolation? What can be going
wrong with the RLOC attribute? Since this is the first time we've ever used
them, I suspect we might be missing something out.

I would appreciate any help,
Sincerely,
Berk

--
Posted via a free Usenet account from http://www.teranews.com

"Berk Birand" <[email protected]> wrote in message
news:[email protected]...
> Hi all,
>
> In our design, we have a sensitive circuitry that we think may be affected
> by the bulk of the circuit (mainly two state machines). In order to
> isolate
> it in a section of the FPGA (Virtex-II Pro XC2VP30), we tried using the
> RLOC and RLOC_ORIGIN attributes. We did manage to group the sensitive
> circuitry, and move it all the way to the bottom-left corner of the chip.
> However, when we do that, the rest of the CLBs also move with them.
>
What do you mean by "sensitive circuit"?

"Berk Birand" <[email protected]> wrote in message
news:[email protected]...
> Hi all,
>
> In our design, we have a sensitive circuitry that we think may be affected
> by the bulk of the circuit (mainly two state machines).
What makes it a 'sensitive circuit'? What is the 'bulk'?

> In order to isolate
> it in a section of the FPGA (Virtex-II Pro XC2VP30), we tried using the
> RLOC and RLOC_ORIGIN attributes. We did manage to group the sensitive
> circuitry, and move it all the way to the bottom-left corner of the chip.
Why isolate it? Have you diagnosed a problem? If so, what is it? Explain
why isolation would help.

> However, when we do that, the rest of the CLBs also move with them.
>
Your 'sensitive circuit' no doubt communicates with other stuff inside that
FPGA. Those things will tend to want to move, which can drag yet other
stuff as well.

> Although we tried to use the RLOC attribute for the rest of the circuit,
> they are somehow not recognized. The reason might be that the files are in
> different hierarchy levels, and the Xilinx Floorplanner doesn't recognize
> the U_SET.
>
> How do you suggest we go about doing this isolation? What can be going
> wrong with the RLOC attribute? Since this is the first time we've ever
> used
> them, I suspect we might be missing something out.
>
First off, I'm guessing that what makes your 'sensitive circuit' sensitive
is timing problems. If that is the case then no amount of manual placement
will help you get to a robust solution. Symptoms of timing problems are:
- Flaky behavior (i.e. sometimes it works, sometimes it doesn't).
- Apparent sensitivity to temperature (it works when it's cold, not after
running for a bit....or vice versa).

If this is what you are classifying as 'sensitive' then I would suggest
first look at the static timing analysis report and fix all the problems.
Also check that all FPGA inputs are properly synchronized to the proper
clock before using them. You made mention of 'two state machines'. Are ALL
of the inputs to those state machines synchronized to the state machine's
clock? A common error is using a signal as input to that state machine that
is not synchronized to the clock...because it doesn't change very
frequently, or some other such nonsense. Inevitably the timing of that
signal violates the setup time and the state machine goes into the wrong
state. Checking async inputs and clock domain crossings are just a subset
of timing analysis (albeit common problems).

If by 'sensitive circuit' you're instead seeing that this sensitive area
works when the rest of the design is somewhat quiescent but then when there
is a 'lot' of activity the design seems to flake out, then this tends to
point to power supply problems where the PCB design has not provided an
adequate power delivery system with its power planes and bypass capacitors.
Solutions here range toward the relatively simple (addding bypass caps) to
'oh @#$%%' where you have to add a power/ground plane or cobble something
together with copper tape and hope.

Bottom line is that unless I've managed to guess correctly at what your
'sensitive circuit' is sensitive to, you're going to need to provide some
more information about this sensitivity. Going about a solution of trying
to do manual placement without a proper understanding of the root cause
problem is simply asking for a lot of pointless work. Going down that path
often results in things magically appearing to 'work'....only to find out
that it 'works' for that board, but not on another.

You've got a broken system, debug that and get to the root cause before
attempting fixes. Broken systems can be debugged, ones that magically start
to 'work' can not and always come back to bite you later.

KJ

"Berk Birand" <[email protected]> wrote in message
news:[email protected]...
> Hi all,
>
> I would appreciate any help,
> Sincerely,
> Berk
>
Hi Berk,
Search for
PROHIBIT

in the xilinx constraints guide. It won't help fix your problem, but what
the hey.

Cheers, Syms.

On 26 Oct 2007 18:42:44 GMT, Berk Birand <[email protected]> wrote:

>Hi all,
>
>In our design, we have a sensitive circuitry that we think may be affected
>by the bulk of the circuit (mainly two state machines). In order to isolate
>it in a section of the FPGA (Virtex-II Pro XC2VP30), we tried using the
>RLOC and RLOC_ORIGIN attributes. We did manage to group the sensitive
>circuitry, and move it all the way to the bottom-left corner of the chip.
>However, when we do that, the rest of the CLBs also move with them.
>
>Although we tried to use the RLOC attribute for the rest of the circuit,
>they are somehow not recognized. The reason might be that the files are in
>different hierarchy levels, and the Xilinx Floorplanner doesn't recognize
>the U_SET.
>
>How do you suggest we go about doing this isolation? What can be going
>wrong with the RLOC attribute? Since this is the first time we've ever used
>them, I suspect we might be missing something out.

RLOC is Relative LOC; it places parts relative to each other but says
nothing about their absolute location. The tools WILL move the groups
around to shorten routes...

You may need to LOC your sensitive circuit in one corner and LOC the
rest in other places; if the rest is large, that's a lot of LOC
constraints.

Look at the Constraints Guide (cgd.pdf) to see how to use the AREA_GROUP
and RANGE constraints.

- Brian