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  #1 (permalink)  
Old 06-03-2009, 01:50 PM
Real SoPC New-Be
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Default Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio

Hello,
I'm working on a system combining a MicroBlaze, memory and some user
RTL logic. I'm not the creator, I've received all the files and I'm
supposed to introduce a few changes... However, I've encountered a
problem. I'll try to describe it.

In the design, there are a few clock signals used, generated by a
clock generator IP. I was supposed to add a new clock signal in the
generator and feed with it a clock input of one of the system
components. I've done it. But... I have to add a constraint for this
new clock in the UCF file. Once I've added a constrained (manually),
I've received an error in Xilinx ISE (clock signal I've added is
unknown). And Xilinx ISE doesn't allow me to add a constraint in GUI
because of the same reason.

What the hell is wrong? Maybe there is a simple obvious thing I don't
know. Anyway, iif you have any idea - please, tell me! Thanks in
advance.

*** ADDITIONAL INFO ***
The exact error message I've received is as follows:

ERROR:ConstraintSystem:59 - Constraint <NET
"MB_SYSTEM/clock_generator_0/clock_generator_0/PLL0_CLK_OUT<5>"
TNM_NET =
MB_SYSTEM/clock_generator_0/clock_generator_0/PLL0_CLK_OUT<5>;>
[MB_ENCODER.ucf(287)]: NET
"MB_SYSTEM/clock_generator_0/clock_generator_0/PLL0_CLK_OUT<5>" not
found.
Please verify that:
1. The specified design element actually exists in the original
design.
2. The specified object is spelled correctly in the constraint
source file.
<end of msg>

As far as I know, the specified design element does actually exist in
the original design!
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  #2 (permalink)  
Old 06-03-2009, 06:09 PM
MM
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Default Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio

Is your top level design in ISE or EDK? Can you post your system.mhs file?


/Mikhail


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  #3 (permalink)  
Old 06-04-2009, 08:52 AM
Real SoPC New-Be
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Default Re: Xilinx ISE doesn't recognize a signal added in Xilinx PlatformStudio

On Jun 3, 6:09*pm, "MM" <[email protected]> wrote:
> Is your top level design in ISE or EDK? Can you post your system.mhs file?
>
> /Mikhail


AFAIK, the top level desing is in ISE. The MHS file is OK, it seems to
reflect changes I've done in XPS'.


# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build
EDK_K_SP3.6

PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
# (...)

# #CLOCKS
PORT CLK_200_MHz = DDR2_SDRAM_16Mx32_mpmc_clk_s, DIR = O, SIGIS = Clk
PORT CLK_166_MHz = DDR2_SDRAM_32Mx64_clk_s, DIR = O, SIGIS = Clk
PORT JP2KE_clk_pin = jp2k_clk_s, DIR = O, SIGIS = CLK
PORT fsl2dvi_jp2kes2fsl_0_odck_rx_pin = fsl2dvi_jp2kes2fsl_0_odck_rx,
DIR = O, SIGIS = Clk

# (...)

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT1_FREQ = 200000000
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = PLL0
PARAMETER C_CLKOUT2_FREQ = 200000000
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT2_PHASE = 90
PARAMETER C_CLKOUT2_GROUP = PLL0
PARAMETER C_CLKIN_BUF = FALSE
PARAMETER C_CLKOUT3_FREQ = 50000000
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = NONE
PARAMETER C_CLKOUT3_BUF = TRUE
PARAMETER C_CLKOUT4_FREQ = 166666667
PARAMETER C_CLKOUT4_PHASE = 0
PARAMETER C_CLKOUT4_GROUP = NONE
PARAMETER C_CLKOUT4_BUF = TRUE
PARAMETER C_CLKOUT5_FREQ = 100000000
PARAMETER C_CLKOUT5_PHASE = 0
PARAMETER C_CLKOUT5_GROUP = NONE
PARAMETER C_CLKOUT5_BUF = TRUE
PORT CLKOUT0 = sys_clk_s
PORT CLKOUT1 = DDR2_SDRAM_16Mx32_mpmc_clk_s
PORT CLKOUT2 = DDR2_SDRAM_16Mx32_mpmc_clk_90_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
PORT CLKOUT3 = DVI_clk_s
PORT CLKOUT4 = DDR2_SDRAM_32Mx64_clk_s
PORT CLKOUT5 = jp2k_clk_s
END

# (...)

As I "view RTL schematic" in ISE, I can see that CLKOUT5 is not
connected, and JP2KE_clk_pin is fed with sys_clk_s (as it was in the
previous version of the project). It is interesting because previously
I could see correct connections in the RTL viewer, and the only
problem (which still exists now) was no ability to add a constraint
for the jp2k_clk_s signal.

The only explanation I can imagine is that the project file(s) became
somehow corrupted, but I feel nervous when I think about building the
entire system again from scratch. The reason for this hipothesis is
the fact that my ISE very often gives a "fatal error" unexpectedly and
closes.

/marteno
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  #4 (permalink)  
Old 06-04-2009, 04:43 PM
MM
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Default Re: Xilinx ISE doesn't recognize a signal added in Xilinx Platform Studio

Marteno,

It sounds as you need to clean your project. Unfortunately, Xilinx tools
aren't reliable in detecting design changes. There are several ways of doing
this. You can do it from ISE Project menu, or you could clean hardware from
the EDK Hardware menu first just to be sure. You could also manually delete
relevant (system.ncd, clock_generator.ncd ) or simply all ncd files from the
directory tree. Note that there is a cache directory where EDK stores copies
of ncd files.


/Mikhail


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  #5 (permalink)  
Old 06-06-2009, 04:18 PM
Marteno Rodia
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Default Re: Xilinx ISE doesn't recognize a signal added in Xilinx PlatformStudio

On Jun 4, 4:43*pm, "MM" <[email protected]> wrote:
> It sounds as you need to clean your project. Unfortunately, Xilinx tools
> aren't reliable in detecting design changes. There are several ways of doing
> this. You can do it from ISE Project menu, or you could clean hardware from
> the EDK Hardware menu first just to be sure. You could also manually delete
> relevant (system.ncd, clock_generator.ncd ) or simply all ncd files from the
> directory tree. Note that there is a cache directory where EDK stores copies
> of ncd files.


Mikhail, thank you, that's it!!

MR
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