This is probably a dumb question, but I'm trying to figure some aspects
of the software (ISE 7.1.4) out.
I have a design for a Virtex-II
FPGA that basically consists of several
data busses and several accumulators (Xilinx Core) which correspond to
the data busses, and some control signals. Basically I'm taking data
in and either adding it to or substracting it from the accumulators.
At this point it's a really simple case where I'm using 1-bit as a
control signal. '1' I add, '0' I substract. Both the control signal
and the data are clocked in by seperate clock signals. Real simple.
The sequence goes:
Control signal valid -> control clock edge -> data valid -> data strobe
Speed is about 5 MHz overall with the signal, clock, signal, clock
sequence basically evenly spaced over that period.
If I basically leave the tools to their own (Xilinx ISE 7.1) what it
basically does is put a flip-flop near the control signal and clock and
fans the output out to the accumulators... Which amounts to something
like 164 internal signals. The auto-routing of the internal signals
ends up as a mess that basically doesn't work.
I can fix it by going into the placement editor and moving the
flip-flop to a logical place near the accumulators so the router ends
up with a more reasonable route. Which is okay, I guess.
My question is how do I specify timing contraints such that the
placement minimizes the route from the output of the flip-flop to the
accumulators?
The other thing I can do is replicate the flip-flop for the control
signal for each accumulator and set ISE to not trim duplicated
registers...
Thanks!