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Old 04-19-2006, 05:24 PM
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Default Xilinx FPGA status after configuration.

Hi all,

I am working with a Xilinx Virtex4 and I have troubles with the "after
configuration" state of the FPGA.

I search on the Xilinx web site and on the web but the only thing I
fond was the module called STARTUP_VIRTEX4 that in my understanding is
used only to put the registers in the defaut state but not to determine
the initial state.

I think that putting initial statements both in the source code or in
the constrain file is not a good solution because the project is
changing day by day and maintain such a thing does not seem to me
really handy.

I had some experience with the Spartan3 family and there a module calle
ROC was provided in order to tell the implementation software that the
initialisation value for all the registers connected to that net was
the one those registers were assigned in the rest condition.

Does anyone of you know if a way exsists to direclty code in the VHDL
the value after configuration?

Pushing a button after configuration is possible but no really elegant,
so I was wondering if someone knows of a circuit able to generate a
reset pulse at power up (after configuration) without knowing the
initial status. It will be the best soltution because it would not be
FPGA family or technology dependent.

Any suggestion is really apprecheated.

Regards,

Andrea

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  #2 (permalink)  
Old 04-19-2006, 06:29 PM
John_H
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Default Re: Xilinx FPGA status after configuration.

If you're working with XST, you may be able to use initial statements for
both simulation *and* synthesis. The only other way to avoid the issues is
to go with an asynchronous reset.


<[email protected]> wrote in message
news:[email protected] oups.com...
> Hi all,
>
> I am working with a Xilinx Virtex4 and I have troubles with the "after
> configuration" state of the FPGA.
>
> I search on the Xilinx web site and on the web but the only thing I
> fond was the module called STARTUP_VIRTEX4 that in my understanding is
> used only to put the registers in the defaut state but not to determine
> the initial state.
>
> I think that putting initial statements both in the source code or in
> the constrain file is not a good solution because the project is
> changing day by day and maintain such a thing does not seem to me
> really handy.
>
> I had some experience with the Spartan3 family and there a module calle
> ROC was provided in order to tell the implementation software that the
> initialisation value for all the registers connected to that net was
> the one those registers were assigned in the rest condition.
>
> Does anyone of you know if a way exsists to direclty code in the VHDL
> the value after configuration?
>
> Pushing a button after configuration is possible but no really elegant,
> so I was wondering if someone knows of a circuit able to generate a
> reset pulse at power up (after configuration) without knowing the
> initial status. It will be the best soltution because it would not be
> FPGA family or technology dependent.
>
> Any suggestion is really apprecheated.
>
> Regards,
>
> Andrea



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  #3 (permalink)  
Old 04-19-2006, 06:37 PM
Guest
 
Posts: n/a
Default Re: Xilinx FPGA status after configuration.

Hi Jonh,

tanks for your suggestion. I am not using XST but only ISE to generate
the bit file and Synopsys FPGA Design compiler to generate the netlist.

The asynchronous reset is fine with me expecially if do not have to
push a button. Any idea how to implement this?

Regards,

Andrea

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