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  #1 (permalink)  
Old 12-02-2005, 08:37 AM
Chloe
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Default Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Calling all FPGA experts!

I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter
6.0a simulator. The FPGA which I am downloading my design onto is a
Spartan IIE (it's on the Spartan IIE LC Development Kit, with an
XC2S300E device).

After synthesizing, implementing and programming the design onto the
FPGA, I tested the outputs of the FPGA on the development kit using a
digital oscilloscope. However, I was not getting the signals I wanted.
After simulating the design on ModelSim, and comparing the simulated
outputs with the actual FPGA outputs, I realised that the behavioral
model of the design was somehow transferred onto the FPGA, instead of
the place-and-routed model.

I checked the synthesis report, but there were no errors. There were
some warnings, but they were unimportant (certain ports were assigned
but not used), thus, neglected at the moment. There were also no timing
violations. I also checked all the reports under "Implement Design",
and there were no errors.

Can anyone tell me why the behavioral model was transferred onto the
FPGA instead of the place-and-routed model? Is that even possible? Can
anyone advise me on the methods of overcoming this problem?

I'd be happy to provide any extra information you need.

Thanks very much in advance.

Regards,
Chloe

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  #2 (permalink)  
Old 12-02-2005, 04:03 PM
Ryan Jones
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Default Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Chloe ,

I am pretty sure it is impossible to have the behavioral model
transferred to the FPGA. When you generate the JTAG file it runs
Translate, MAP and PAR first. Most likely, you are using modelsim with
the behavioral model instead of the place and route model. Make sure
you choose simulate post place and route model in your testbench. If
you are then there is some timing discrepency that modelsim is not
noticing that is causing the outputs of the FPGA to differ. Another
possibility is to make sure that you are not loading an old programming
file. This is a common problem. Regenerate the program file, noting the
time when it ran, and make sure the file you program is timestamped
with the same time.

Ryan

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  #3 (permalink)  
Old 12-03-2005, 03:46 PM
John Adair
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Default Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Chloe

You left out a few facts that might help the group understand where your
problem has come from.

(1) The behavoural model - was this a simulation output from ISE e.g. post
translate model or one that you have written independently?

(2) Did your model have signals relationships defined by timing
relationships or by clock edges? Could it have been a model that might
synthesise?

(3) Do you have a macro (edif, ngc etc) that ISE might have picked up
instead of the behavioural model? Translate report should tell you that.

One thing to check is that you are not picking up a locally stored copy
rather than one from a remote directory if that is what you are expecting.
One trick if you are getting the unxpected is to change something in the
design file that you can easily monitor in the real world, e.g. output your
internal clock to a pin, and if that does not happen you know you are
picking up something unexpected.

Another thing to check is if increment synthesis is turned off in XST. There
have been issues with this I believe. Finally if you have not loaded any
service packs you should do so. Service pack 4 is the latest and can be
loaded direct without loading any of the prior service packs.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The Low Cost FPGA Development Board.
http://www.enterpoint.co.uk


"Chloe" <[email protected]> wrote in message
news:[email protected] oups.com...
> Calling all FPGA experts!
>
> I'm currently using Xilinx ISE 7.1i with the ModelSim XE III/Starter
> 6.0a simulator. The FPGA which I am downloading my design onto is a
> Spartan IIE (it's on the Spartan IIE LC Development Kit, with an
> XC2S300E device).
>
> After synthesizing, implementing and programming the design onto the
> FPGA, I tested the outputs of the FPGA on the development kit using a
> digital oscilloscope. However, I was not getting the signals I wanted.
> After simulating the design on ModelSim, and comparing the simulated
> outputs with the actual FPGA outputs, I realised that the behavioral
> model of the design was somehow transferred onto the FPGA, instead of
> the place-and-routed model.
>
> I checked the synthesis report, but there were no errors. There were
> some warnings, but they were unimportant (certain ports were assigned
> but not used), thus, neglected at the moment. There were also no timing
> violations. I also checked all the reports under "Implement Design",
> and there were no errors.
>
> Can anyone tell me why the behavioral model was transferred onto the
> FPGA instead of the place-and-routed model? Is that even possible? Can
> anyone advise me on the methods of overcoming this problem?
>
> I'd be happy to provide any extra information you need.
>
> Thanks very much in advance.
>
> Regards,
> Chloe
>



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  #4 (permalink)  
Old 12-07-2005, 06:28 AM
Chloe
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Posts: n/a
Default Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Thanks very much for your replies and suggestions.

At this moment, I do not have the development kit with me, so I cannot
continue testing of my design on the FPGA. Thus, any changes I make
cannot be programmed and checked. When I get the board back from my
colleagues, I'll try out your suggestions at once.

Ryan,
I do understand what you mean. That's why I thought it was baffling
that the behavioural model was transferred onto the FPGA, because I ran
Translate, MAP and PAR. I simulated all verilog models (behavioural,
post-translate, post-map and post-PAR). The post-translate, post-map
and post-PAR simulations results were the same, but they differ from
the behavioural model. Initially, when I tested the outputs using a
digital oscilloscope, the results I got seemed to match the behavioural
model, and not the post-translate, model or PAR.

John,
To answer your questions,
(1) I'm not sure if I understood your first question but all verilog
models were simulation output from ISE. The behavioural model follows
the RTL which I wrote.

(2) Yes, my model has signal relationsips defined by clock edges. The
models synthesised OK. There were several warnings, but the severity is
very low.

(3) It read an NGC file. I'm afraid I do not know what this means,
because I'm very new at FPGAs and hardware design. Please see below for
the translation report:

---------------

Command Line: ngdbuild -intstyle ise -dd c:\rtl_fpga/_ngo -uc test.ucf
-p
xc2s300e-fg456-6 test.ngc test.ngd
Reading NGO file 'C:/rtl_fpga/test.ngc' ...
Applying constraints in "test.ucf" to the design...
Checking timing specifications ...
Checking expanded design ...
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 53236 kilobytes
Writing NGD file "test.ngd" ...
Writing NGDBUILD log file "test.bld"...

-----------------

I did output the internal clocks to pins to monitor the results. The
internal clocks and signals work OK, but the outputs were not as
expected.


Unfortunately, I encountered another problem. Like I mentioned before,
I currently do not have the FPGA development board with me, so I can't
continue to do any checking of signals. I made some changes to the
design in RTL, and after synthesis, translate, map and PAR, I ran a
simulation on all the verilog models. The behavioural model worked as
expected. However, the post-translate, map and PAR models were wrong.
There were no errors nor timing violations during synthesis. There were
also no errors in design translate, map and PAR. Could the problem be
in my pin assignment? There were no errors there though. I didn't use
the Xilinx PACE, but LOCed my input/output pins instead.

Any suggestions? Please feel free to ask for any more information, as I
do not know what to add, as I did not encounter any errors. Again,
please forgive the triviality of the questions as I am very new to
this.

Thanks very much in advance for all your help. Appreciated

Chloe

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  #5 (permalink)  
Old 12-07-2005, 07:15 AM
Chloe
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Posts: n/a
Default Re: Xilinx FPGA - Behaviorial Model Transferred Instead of Place-and-routed Model

Oh, by the way, I did get this in my Post-translate Simulation Model
report:

Command Line: netgen -intstyle ise -sdf_anno true -w -ofmt verilog -sim
test.ngd test_translate.v

WARNING:NetListWriters:550 - Ignoring non-applicable option -sdf_anno
for input
file with 'ngd' extension.
Reading design 'test.ngd' ...

Can anyone tell me if that's wrong?

Thanks in advance.

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