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Old 04-24-2006, 08:09 AM
Antti
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Default Xilinx EDK 8.1 DDR controller behavior

Hi

does anyone know what should happen on read access to DDR
memory space when external connections to DDR memory
are not correct? I am troubleshooting a custom board and
what I see is that OPB DDR controller makes total OPB bus
freeze on first DDR read access. ToutSup=1 and then nothing
happens. In the datasheet DQS strobe is going to WREN of
read fifo so I could think a missing DQS from external chip could
cause bus freeze, but I am not really sure as it is not described
in the datasheet (eg what should happen on missing DQS).

I have tried all DDR controllers from EDK 8.1
PLB_DDR
OPB_DDR
OPB_MCH_DDR
and all seem to have similar freeze behaviour
the DCMs all work (tested) and the EDK system
also works - well until first read to DDR space

any helpful hints?

Antti

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Old 04-24-2006, 05:54 PM
John
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Default Re: Xilinx EDK 8.1 DDR controller behavior

Antti

When you get a timeout the OPB bus master should release the bus removing
"SELECT" and other signals from active to their inactive state of all "0"s.
I'm guessing the DDR module isn't passing back the XFERACK as expected.

If you have done this manually check the timeout signals are wired into the
array correctly.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk


"Antti" <[email protected]> wrote in message
news:[email protected] oups.com...
> Hi
>
> does anyone know what should happen on read access to DDR
> memory space when external connections to DDR memory
> are not correct? I am troubleshooting a custom board and
> what I see is that OPB DDR controller makes total OPB bus
> freeze on first DDR read access. ToutSup=1 and then nothing
> happens. In the datasheet DQS strobe is going to WREN of
> read fifo so I could think a missing DQS from external chip could
> cause bus freeze, but I am not really sure as it is not described
> in the datasheet (eg what should happen on missing DQS).
>
> I have tried all DDR controllers from EDK 8.1
> PLB_DDR
> OPB_DDR
> OPB_MCH_DDR
> and all seem to have similar freeze behaviour
> the DCMs all work (tested) and the EDK system
> also works - well until first read to DDR space
>
> any helpful hints?
>
> Antti
>



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  #3 (permalink)  
Old 04-24-2006, 06:05 PM
Sylvain Munaut
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Posts: n/a
Default Re: Xilinx EDK 8.1 DDR controller behavior

Antti wrote:
> Hi
>
> does anyone know what should happen on read access to DDR
> memory space when external connections to DDR memory
> are not correct? I am troubleshooting a custom board and
> what I see is that OPB DDR controller makes total OPB bus
> freeze on first DDR read access. ToutSup=1 and then nothing
> happens. In the datasheet DQS strobe is going to WREN of
> read fifo so I could think a missing DQS from external chip could
> cause bus freeze, but I am not really sure as it is not described
> in the datasheet (eg what should happen on missing DQS).


It freeze ... ie, never acks the transfer.

We use the ddr controller from EDK (without any ipic/ipif, just the
bare controller that's common to plb_ddr, opb_ddr & co) and
if the phase shift of the second dcm is off, it never acks and
thus freeze.


Sylvain
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  #4 (permalink)  
Old 04-24-2006, 11:04 PM
Antti Lukats
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Default Re: Xilinx EDK 8.1 DDR controller behavior

"Sylvain Munaut" <[email protected]> schrieb im
Newsbeitrag news:[email protected]
> Antti wrote:
>> Hi
>>
>> does anyone know what should happen on read access to DDR
>> memory space when external connections to DDR memory
>> are not correct? I am troubleshooting a custom board and
>> what I see is that OPB DDR controller makes total OPB bus
>> freeze on first DDR read access. ToutSup=1 and then nothing
>> happens. In the datasheet DQS strobe is going to WREN of
>> read fifo so I could think a missing DQS from external chip could
>> cause bus freeze, but I am not really sure as it is not described
>> in the datasheet (eg what should happen on missing DQS).

>
> It freeze ... ie, never acks the transfer.
>
> We use the ddr controller from EDK (without any ipic/ipif, just the
> bare controller that's common to plb_ddr, opb_ddr & co) and
> if the phase shift of the second dcm is off, it never acks and
> thus freeze.
>
>
> Sylvain


thanks!

this is what I guessed too, just wanted confirmation that it really
freezes when no DQS on reads are seen.

Antti


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