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  #1 (permalink)  
Old 01-07-2004, 10:36 PM
Alex Rast
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Default Xilinx ECS - connecting a single net to multiple bus lines?

What's the way to do this? It's common for me to run into situations where
I have a bus or bus pin, and I need to connect the same net to different
lines on the bus. Another common one is I have 2 busses, both of which have
a line that should connect to a single net. The documentation doesn't seem
to give any hints. Thanks for any input.

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  #2 (permalink)  
Old 01-10-2004, 10:53 AM
Philip Freidin
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Default Re: Xilinx ECS - connecting a single net to multiple bus lines?

On Wed, 07 Jan 2004 21:36:15 -0000, [email protected] (Alex Rast) wrote:

A)
>What's the way to do this? It's common for me to run into situations where
>I have a bus or bus pin, and I need to connect the same net to different
>lines on the bus.


B)
>Another common one is I have 2 busses, both of which have
>a line that should connect to a single net. The documentation doesn't seem
>to give any hints. Thanks for any input.


While I have not used ECS, the way we did this in previous schematic
systems was to pass the source single through multiple "BUF" symbols.

Look in the libraries guide:

http://toolbox.xilinx.com/docsan/xil...ks/manuals.htm

Libraries Guide -> Design Elements -> BUF

A) sourcenet -> BUF -> dest_bus_[2]
sourcenet -> BUF -> dest_bus_[3]

B) SourceBusBit_[3] -> BUF -> DestBusBit_[6]

The BUF is a primitive that uses no logic resources. It is used to alias
one signal name to another, and is trimmed out during the P&R process


Philip



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  #3 (permalink)  
Old 01-12-2004, 12:43 AM
Hal Murray
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Default Re: Xilinx ECS - connecting a single net to multiple bus lines?

>What's the way to do this? It's common for me to run into situations where
>I have a bus or bus pin, and I need to connect the same net to different
>lines on the bus. Another common one is I have 2 busses, both of which have
>a line that should connect to a single net. The documentation doesn't seem
>to give any hints. Thanks for any input.


What does "connect the same net to different lines on the bus" mean?

Do you want a mux or tri-state driver, to read a status bit when a
particular register is selected? Or do you want a solid connection
100% of the time?

If you want a hard connection, then physically, you are merging
several nets into one. That seems a bit strange if two of them
are part of the same bus.

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  #4 (permalink)  
Old 01-13-2004, 02:27 AM
Alex Rast
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Default Re: Xilinx ECS - connecting a single net to multiple bus lines?

at Sat, 10 Jan 2004 09:53:18 GMT in
<[email protected]>, [email protected]
(Philip Freidin) wrote :

>On Wed, 07 Jan 2004 21:36:15 -0000, [email protected] (Alex
>Rast) wrote:
>
>A)
>>What's the way to do this? It's common for me to run into situations
>>where I have a bus or bus pin, and I need to connect the same net to
>>different lines on the bus.

>
>B)
>>Another common one is I have 2 busses, both of which have
>>a line that should connect to a single net. The documentation doesn't
>>seem to give any hints. Thanks for any input.

>
>While I have not used ECS, the way we did this in previous schematic
>systems was to pass the source single through multiple "BUF" symbols.
>...
>The BUF is a primitive that uses no logic resources. It is used to alias
>one signal name to another, and is trimmed out during the P&R process


It seems stupidly cumbersome to have to do this. Since I'm not thrilled
(read "mistrust the software" about relying on something to be trimmed out
during P&R - incidentally, why do no S/W packages seem to want to allow an
easy way for you to define P&R manually, when P&R is the one thing that a
computer does the least well - so I created the following general-purpose
VHDL "component"

entity ConnectLine2Bus is
Generic (BusWidth : integer := 8);
Port (
InputSignal : in std_logic;
OutputBus : out std_logic_vector((Buswidth-1) downto 0));
end ConnectLine2Bus;

architecture StraightThrough of ConnectLine2Bus is

signal ConnectInt : std_logic;

begin

ConnectInt <= InputSignal;
ConnectSignals: for LineNo in 0 to (Buswidth-1) generate
OutputBus(LineNo) <= ConnectInt;
end generate;

end StraightThrough;

and then used the "Generate Schematic symbol" to create a symbol for it.
You can then make connections of arbitrary size, which works nicely and as
you can see from the VHDL description, I'm simply wiring straight through.

Still, the whole thing seems ridiculous, IMHO something Xilinx should fix
in future revisions.

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  #5 (permalink)  
Old 01-14-2004, 01:35 AM
Marc Guardiani
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Posts: n/a
Default Re: Xilinx ECS - connecting a single net to multiple bus lines?

One can also do this by reference using a "cat bus". For example,
suppose you have the named signals, A, B, and C. You can create an 8-bit
bus by naming it:
"A,B,B,C,A,A,A,C" (remove quotes, can't remember if you might need
parenthesis around the whole mess)


Philip Freidin wrote:

> On Wed, 07 Jan 2004 21:36:15 -0000, [email protected] (Alex Rast) wrote:
>
> A)
>
>>What's the way to do this? It's common for me to run into situations where
>>I have a bus or bus pin, and I need to connect the same net to different
>>lines on the bus.

>
>
> B)
>
>>Another common one is I have 2 busses, both of which have
>>a line that should connect to a single net. The documentation doesn't seem
>>to give any hints. Thanks for any input.

>
>
> While I have not used ECS, the way we did this in previous schematic
> systems was to pass the source single through multiple "BUF" symbols.
>

<snip>
>
> Philip
>
>
>
> ===================
> Philip Freidin
> [email protected]
> Host for WWW.FPGA-FAQ.COM


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