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Old 11-24-2007, 06:46 PM
naresh
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Default Xilinx Dual processor design

Hi all
I am using Xilinx dual processor reference design suite to develop
dual processor (xapp996) system on virtex-2 pro.
I want to port an operating system on to this design
Is it possible to port an OS that uses this dual-core system.
Please help if anybody worked with this reference design

Thanks
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  #2 (permalink)  
Old 11-25-2007, 09:35 PM
Ben Jackson
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Default Re: Xilinx Dual processor design

On 2007-11-24, naresh <[email protected]> wrote:
> Is it possible to port an OS that uses this dual-core system.


I think the biggest obstacle is lack of hardware cache coherency.
There's a big Xilinx appnote on 2 PPC setups, though:

http://www.xilinx.com/support/docume...pers/wp262.pdf

--
Ben Jackson AD7GD
<[email protected]>
http://www.ben.com/
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  #3 (permalink)  
Old 11-27-2007, 08:46 AM
Andreas Hofmann
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Default Re: Xilinx Dual processor design

naresh schrieb:
> I am using Xilinx dual processor reference design suite to develop
> dual processor (xapp996) system on virtex-2 pro.
> I want to port an operating system on to this design
> Is it possible to port an OS that uses this dual-core system.


That depends on your operating system. The PPC405 has no support for
cache coherency so a system with physically shared memory can't use the
caches out of the box. If you're only using the on-chip BRAMs this won't
make much a difference. If you have to use external memory it will kill
your performance.

Maybe there is a way to implement a mixed hardware/software support for
cache coherency. Building a module to snoop the memory buses of the
PPC405s shouldn't be much of a problem but you have to be sure that you
see all memory transactions. Bad luck if the cache is write-back.

So all in all throwing Linux with a SMP kernel on it won't work.

Depending on your requirements you can run two instances of the
xilkernel, one on each of the PPC405s. Those systems can communicate
with a shared PLB-memory block and control access to other modules with
the opb_mutex.

Best regards,
Andreas
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  #4 (permalink)  
Old 12-14-2007, 07:51 AM
Andreas Ehliar
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Default Re: Xilinx Dual processor design

On 2007-11-27, Andreas Hofmann <[email protected]> wrote:
> naresh schrieb:
>> I am using Xilinx dual processor reference design suite to develop
>> dual processor (xapp996) system on virtex-2 pro.
>> I want to port an operating system on to this design
>> Is it possible to port an OS that uses this dual-core system.

>
> That depends on your operating system. The PPC405 has no support for
> cache coherency so a system with physically shared memory can't use the
> caches out of the box. If you're only using the on-chip BRAMs this won't
> make much a difference. If you have to use external memory it will kill
> your performance.
>
> Maybe there is a way to implement a mixed hardware/software support for
> cache coherency. Building a module to snoop the memory buses of the
> PPC405s shouldn't be much of a problem but you have to be sure that you
> see all memory transactions. Bad luck if the cache is write-back.
>
> So all in all throwing Linux with a SMP kernel on it won't work.


Something I have been thinking about is modifying the Linux kernel so that
one of the processors act as a master processor with full access to the
entire system and also the possibility to allocate the second processor
as a slave processor. If the slave processor wants to make a system call,
all the caches have to be flushed, so this should obviously not be done
lightly, but it might be a perfect setup where one of the processors is used
for general OS management, UI, etc and one of the processors is used for
real-time tasks, etc, while still retaining the impression of a relatively
friendly programming environment for the slave processor.

There would also have to be some additional restrictions on the second
processor. mmap() could present a problem for example.

/Andreas
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  #5 (permalink)  
Old 12-17-2007, 11:31 AM
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Default Re: Xilinx Dual processor design

Hi,

I'm actually working in a port of xilkernel for SMP systems. It
actually works with 2 to 8 MicroBlazes, but I haven't ported it to PPC
yet.
Performance is not as good as expected due to the impossibility of
using data caches.

For using with PPC I think you can use eCos, that has support for
PowerPC and SMP systems, but I have never used it.

Regards,

Pablo H


On 24 nov, 19:46, naresh <[email protected]> wrote:
> Hi all
> I am using Xilinx dual processor reference design suite to develop
> dual processor (xapp996) system on virtex-2 pro.
> I want to port an operating system on to this design
> Is it possible to port an OS that uses this dual-core system.
> Please help if anybody worked with this reference design
>
> Thanks


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