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Old 01-18-2006, 12:13 PM
Mahmoud
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Default Xilinx 8.1i: Testbench waveform from VHDL netlist does not work ??

In ISE 8.1i creating a Testbench waveform does not work for a Schematic
TOP Level project with VHDL set as the language for HDL Functional
Language Model (Verilog is the default, in 8.1i the Simulation
generated language option was removed from the project properties)

Testbench waveform works for Verilog netlist and it works in 7.1i for
VHDL too. I tried 8.1i SP1 but it did not help.

Does anyone have the same problem?

Thanks

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