FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-24-2006, 09:40 PM
potter
Guest
 
Posts: n/a
Default XDL router info needed

hi ALL!!

i have a small query, FPGA geeks help me plz...

I have a question on the XDL report, i am acually trying to move a
circuit by modifying the XDL file, btw i am using a Virtex II FPGA.

i have been successful in moving the slices and the pins to differnt
locartion but not the routers, i was able to decode the slice info.,
but not the routrers information. Please help me in decoding the
routers info.

i have attached a small report on the routers info from the XDL file,
the info that i have attached it the output net of the 2 input AND
gate.
================================================== =====
net "Z_OBUF" ,
inpin "Z" O1 ,
outpin "Z_OBUF" Y ,
pip R17C1 Y3 -> OMUX10 ,
pip LIOIR16 OMUX_NW10 -> IOIS_FAN_BX2 ,
pip LIOIR16 IOIS_FAN_BX2 -> O1_B1 ,
;
================================================== =======

i want information on OMUX, FAN_BX2, and where i can get info on them,
please help me with the routers info, i am stranded with this for the
past 3 days.
i will thanful if you could throw some light on it.

A speedy reply will be appreciated.

Reply With Quote
  #2 (permalink)  
Old 05-02-2006, 07:28 AM
Markus
Guest
 
Posts: n/a
Default Re: XDL router info needed

potter wrote:
> hi ALL!!
>
> i have a small query, FPGA geeks help me plz...
>
> I have a question on the XDL report, i am acually trying to move a
> circuit by modifying the XDL file, btw i am using a Virtex II FPGA.
>
> i have been successful in moving the slices and the pins to differnt
> locartion but not the routers, i was able to decode the slice info.,
> but not the routrers information. Please help me in decoding the
> routers info.
>
> i have attached a small report on the routers info from the XDL file,
> the info that i have attached it the output net of the 2 input AND
> gate.
> ================================================== =====
> net "Z_OBUF" ,
> inpin "Z" O1 ,
> outpin "Z_OBUF" Y ,
> pip R17C1 Y3 -> OMUX10 ,
> pip LIOIR16 OMUX_NW10 -> IOIS_FAN_BX2 ,
> pip LIOIR16 IOIS_FAN_BX2 -> O1_B1 ,
> ;
> ================================================== =======
>
> i want information on OMUX, FAN_BX2, and where i can get info on them,
> please help me with the routers info, i am stranded with this for the
> past 3 days.
> i will thanful if you could throw some light on it.


You can create a complete device description with xdl:

e.g.: xdl -report -pips v50pq240-5 v50pq240-5.xdlrc

It contains also information about the routing fabric. Beware, the file
becomes awfully large

-Markus
Reply With Quote
  #3 (permalink)  
Old 05-02-2006, 07:24 PM
Superman
Guest
 
Posts: n/a
Default Re: XDL router info needed

Hey Markus,

thanx for the info...I did print this *.xdlrc before, but dint quiet understand the pips connection, would it be possible for u to explain me a little bit, i have understood the OMUX, IMUX, etc, but not the FAN_BX2...IOIS_BX2 etc....can you help me...

thanx in advance
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Design of a Router O. Olson Verilog 8 07-08-2008 04:13 AM
Analog FPGA Project -- VIdeo Router [email protected] FPGA 3 02-24-2006 12:02 AM
Example of network router and # of LUTs utilized - Searching for 3rd party compilation of "typical" specs Jenn Lee FPGA 1 08-11-2004 02:50 AM
Why is router software not multi-threaded? Peter Sommerfeld FPGA 5 01-23-2004 12:18 AM


All times are GMT +1. The time now is 09:40 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved