FPGA Central

Hi All,

I have writen an IP core which is used for implementing an algorithm. Now I have to write the driver for my IP core which mainly transfers the data between the ip core and the plb bus.

But I don't know how to write a driver for an IP CORE. I don't have any related materials.

Who has the experiences of writing the drivers for your own IP core or has some documents about it?

Please help me.

Thank you very much.

Athena wrote:
> Hi All,
>
> I have writen an IP core which is used for implementing an algorithm. Now I have to write the driver for my IP core which mainly transfers the data between the ip core and the plb bus.
>
> But I don't know how to write a driver for an IP CORE. I don't have any related materials.
>
> Who has the experiences of writing the drivers for your own IP core or has some documents about it?
>
> Please help me.
>
> Thank you very much.

Well, since you are going to write drivers for cores connected to the
PLB I suspect that you do have the EDK. There is a 'Device Driver
Programming Guide' in the Processor IP Reference Guide which gives you
the basic knowledge. You also have quite a few drivers in the
../EDK/sw/XilinxProcessorIPLib/drivers catalog of your EDK installation.
I've used them as examples when I have learned to write device drivers
for EDK. The included drivers in the EDK also gives you an idea on how
to write the .mdd and .tcl files.

Good luck.

cheers!

--
-----------------------------------------------
Johan Bernspång, [email protected]
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

Hmm.....


Is you question that you don't how how to format your c functions so
they conform to the Xilinx Driver 'standard'

or....

Is your problem that you don't know how to access your hardware at a
low-level?

-Eli



Johan Bernspång wrote:
> Athena wrote:
>
>> Hi All,
>>
>> I have writen an IP core which is used for implementing an algorithm.
>> Now I have to write the driver for my IP core which mainly transfers
>> the data between the ip core and the plb bus.
>>
>> But I don't know how to write a driver for an IP CORE. I don't have
>> any related materials.
>>
>> Who has the experiences of writing the drivers for your own IP core or
>> has some documents about it?
>>
>> Please help me.
>>
>> Thank you very much.
>
>
> Well, since you are going to write drivers for cores connected to the
> PLB I suspect that you do have the EDK. There is a 'Device Driver
> Programming Guide' in the Processor IP Reference Guide which gives you
> the basic knowledge. You also have quite a few drivers in the
> ./EDK/sw/XilinxProcessorIPLib/drivers catalog of your EDK installation.
> I've used them as examples when I have learned to write device drivers
> for EDK. The included drivers in the EDK also gives you an idea on how
> to write the .mdd and .tcl files.
>
> Good luck.
>
> cheers!
>

Read 'Designing a Custom Processor Peripheral Using Xilinx EDK' - Part
3 and Part 4 available on the Xilinx website under techxclusives.
You'll get what you need.

Hi all,

Thank you for all your suggestions.

I have both ISE and EDK7.0.1. At first, I don't have any conception about how to connect my IP CPRE with the plb or opb bus. I just know one side is the ip core written in VHDL, and the other side should be some driver written in C.

I have read the drivers of Uartlite and spi, but I still couldn't be clear about how to connet the two sides. How to get the .tcl files?

The articles suggested by Kunal are very good. I am reading them at present. I will discuss my thinking with you later.

Thanks to all of you! Athena

The "Create and Import Peripheral Wizard" (chapter 4:
http://www.xilinx.com/ise/embedded/est_rm.pdf) is a good starting
point. Use the skeleton files created as a starting point for your own
custom core. An example device driver to access the custom core from
the procossor is generated as well.

Paul

Athena wrote:
>
> Hi all,
>
> Thank you for all your suggestions.
>
> I have both ISE and EDK7.0.1. At first, I don't have any conception about how to connect my IP CPRE with the plb or opb bus. I just know one side is the ip core written in VHDL, and the other side should be some driver written in C.
>
> I have read the drivers of Uartlite and spi, but I still couldn't be clear about how to connet the two sides. How to get the .tcl files?
>
> The articles suggested by Kunal are very good. I am reading them at present. I will discuss my thinking with you later.
>
> Thanks to all of you! Athena