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Old 10-01-2009, 05:24 PM
Dale
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Default Why won't Xilinx use an FDR?

Hello,
I'm baffled as to why XST won't synthesize this using an FDR making
use of the synchronous reset pin. Instead it's using an FDE and
ANDing the reset with the Data. The problem is that it's hurting my
timing. How can I force XST to use the FDR instead of this kludgy
thing it's doing? And I'd rather not have to explicitly instantiate
an FDR primitive. Below is my coding example.
Thanks,
Dale


process(clk) is
begin
if (clk='1' and clk'event and clk_en = '1') then
if (reset=Pol) then
stored <= (others => '0');
elsif (control = '1') then
stored <= d;
end if;
end if;
end process;
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  #2 (permalink)  
Old 10-01-2009, 05:48 PM
Rob Gaddi
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Default Re: Why won't Xilinx use an FDR?

On Thu, 1 Oct 2009 08:24:44 -0700 (PDT)
Dale <[email protected]> wrote:

> Hello,
> I'm baffled as to why XST won't synthesize this using an FDR making
> use of the synchronous reset pin. Instead it's using an FDE and
> ANDing the reset with the Data. The problem is that it's hurting my
> timing. How can I force XST to use the FDR instead of this kludgy
> thing it's doing? And I'd rather not have to explicitly instantiate
> an FDR primitive. Below is my coding example.
> Thanks,
> Dale
>
>
> process(clk) is
> begin
> if (clk='1' and clk'event and clk_en = '1')
> then if (reset=Pol) then
> stored <= (others => '0');
> elsif (control = '1') then
> stored <= d;
> end if;
> end if;
> end process;


It's giving you what you've asked it for. You've asked for the reset
input to be active only when (clk_en='1'). But the actual reset pin, on
the actual flop, supercedes the enable pin.

If this logic is right, it can't be done the way you want it to. You'd
have to put an AND gate driving the reset pin. There's no dedicated
fast path to do that, so you'd get an AND gate in a different slice,
and then a trip through general routing to take it into the reset, and
that'll slaughter your timing.

Also, if Pol isn't a constant at compile time, then you've also added
an XNOR into the reset path. Same problem as above.

What makes you think that your timing situation would be improved
substantially by not going through the LUT for the reset logic? The
difference between a trip through the LUT, and going around it into the
D input of the flop is, if I recall, on the order of 300ps. Are your
margins really that tight?

--
Rob Gaddi, Highland Technology
Email address is currently out of order
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  #3 (permalink)  
Old 10-01-2009, 05:49 PM
gabor
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Posts: n/a
Default Re: Why won't Xilinx use an FDR?

On Oct 1, 11:24*am, Dale <[email protected]> wrote:
> Hello,
> I'm baffled as to why XST won't synthesize this using an FDR making
> use of the synchronous reset pin. *Instead it's using an FDE and
> ANDing the reset with the Data. *The problem is that it's hurting my
> timing. *How can I force XST to use the FDR instead of this kludgy
> thing it's doing? *And I'd rather not have to explicitly instantiate
> an FDR primitive. *Below is my coding example.
> Thanks,
> Dale
>
> * * * * * * * * process(clk) is
> * * * * * * * * * * * * begin
> * * * * * * * * * * * * if (clk='1' and clk'event and clk_en = '1') then
> * * * * * * * * * * * * * * * * if (reset=Pol) then
> * * * * * * * * * * * * * * * * * * * * stored <= (others => '0');
> * * * * * * * * * * * * * * * * elsif (control = '1') then
> * * * * * * * * * * * * * * * * * * * * stored <= d;
> * * * * * * * * * * * * * * * * end if;
> * * * * * * * * * * * * end if;
> * * * * * * * * end process;


I'm pretty sure that FDR does not apply the clock enable to
the reset input. If you had:

process(clk) is
begin
if (clk='1' and clk'event) then
if (reset=Pol) then
stored <= (others => '0');
elsif (control = '1' and clk_en = '1') then
stored <= d;
end if;
end if;
end process;

you might be able to use an FDR.
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