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Old 04-08-2006, 11:24 AM
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Default Why does Synplify add clock buffers?

I have an Actel design with a 3 clocks. I need to define two of them in
Synplify (v8.5):

define_clock -name {n:clk2} -freq 20
define_clock -name {n:clk1} -freq 100


This will make Synplify to insert clock buffers in the design:

clk2_keep : CLKINT port map(A => clk2_i, Y => clk2);



The problem is that the Actel PAR tool "Designer" (v7.1) doesn't like
these buffers as it will assign the clocks to global clock networks
anyway:

Error: CMP601: This design has a CLKINT instance 'clk2_keep' driven by
a clock net which is not needed. Before compiling this design, this
macro must be removed from the design.


How do i get rid of them? I tried to fix this by setting the max fanout
to a very high value:
define_attribute {n:clk1} syn_maxfan {200000}
define_attribute {n:clk2} syn_maxfan {200000}

but it didnt work


Designer has an option for removing unsued buffers, but I never get to
the optimization stage. Any suggestions how i can stop Synplify from
inserting clock buffers or get Designer to ignore the buffer?

regards,
- Burns



PS. here are the rest of the constraints

forward annotated from Synplify to Designer (as SDC constraints):
create_clock -period 50 -waveform {0.000000 25.00000} clk2
create_clock -period 10 -waveform {0.000000 5.00000} clk1



additional PDC constraints imported to Designer:
assign_global_clock -net {clk2}
assign_global_clock -net {clk1}

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  #2 (permalink)  
Old 04-08-2006, 05:59 PM
Duane Clark
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Default Re: Why does Synplify add clock buffers?

[email protected] wrote:
> I have an Actel design with a 3 clocks. I need to define two of them in
> Synplify (v8.5):
>
> define_clock -name {n:clk2} -freq 20
> define_clock -name {n:clk1} -freq 100
>
>
> This will make Synplify to insert clock buffers in the design:
>
> clk2_keep : CLKINT port map(A => clk2_i, Y => clk2);
>
>
>
> The problem is that the Actel PAR tool "Designer" (v7.1) doesn't like
> these buffers as it will assign the clocks to global clock networks
> anyway:
>
> Error: CMP601: This design has a CLKINT instance 'clk2_keep' driven by
> a clock net which is not needed. Before compiling this design, this
> macro must be removed from the design.
>
>
> How do i get rid of them? I tried to fix this by setting the max fanout
> to a very high value:
> define_attribute {n:clk1} syn_maxfan {200000}
> define_attribute {n:clk2} syn_maxfan {200000}
>
> but it didnt work
>


I don't have version 8.5 of Synplify, but the rather old version I have
has the attribute syn_noclockbuf for this purpose.
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  #3 (permalink)  
Old 04-08-2006, 06:22 PM
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Default Re: Why does Synplify add clock buffers?


That was actually the first thing that I tired.

Needless to say, it did not work

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  #4 (permalink)  
Old 04-08-2006, 07:20 PM
Duane Clark
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Posts: n/a
Default Re: Why does Synplify add clock buffers?

[email protected] wrote:
> That was actually the first thing that I tired.
>
> Needless to say, it did not work
>


It works fine for me on Xilinx parts, so that would appear to be a
regression in Synplify if it doesn't work in the version you have. Or
perhaps it is a problem in the Actel synthesis. It shows up in the
project.sdf file like this:

define_attribute {CLK} syn_noclockbuf {1}

With the attribute set to '1', the edf file contains:

(instance CLK_ibuf (viewRef PRIM (cellRef IBUF (libraryRef VIRTEX)))
)

With the attribute set to '0':
(instance CLK_ibuf (viewRef PRIM (cellRef BUFGP (libraryRef VIRTEX)))
)
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  #5 (permalink)  
Old 04-10-2006, 10:38 AM
Alan Myler
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Posts: n/a
Default Re: Why does Synplify add clock buffers?



[email protected] wrote:

> I have an Actel design with a 3 clocks. I need to define two of them in
> Synplify (v8.5):
>
> define_clock -name {n:clk2} -freq 20
> define_clock -name {n:clk1} -freq 100
>
>
> This will make Synplify to insert clock buffers in the design:
>
> clk2_keep : CLKINT port map(A => clk2_i, Y => clk2);
>
>
>
> The problem is that the Actel PAR tool "Designer" (v7.1) doesn't like
> these buffers as it will assign the clocks to global clock networks
> anyway:
>
> Error: CMP601: This design has a CLKINT instance 'clk2_keep' driven by
> a clock net which is not needed. Before compiling this design, this
> macro must be removed from the design.
>
>
> How do i get rid of them? I tried to fix this by setting the max fanout
> to a very high value:
> define_attribute {n:clk1} syn_maxfan {200000}
> define_attribute {n:clk2} syn_maxfan {200000}
>
> but it didnt work
>
>
> Designer has an option for removing unsued buffers, but I never get to
> the optimization stage. Any suggestions how i can stop Synplify from
> inserting clock buffers or get Designer to ignore the buffer?
>
> regards,
> - Burns
>
>
>
> PS. here are the rest of the constraints
>
> forward annotated from Synplify to Designer (as SDC constraints):
> create_clock -period 50 -waveform {0.000000 25.00000} clk2
> create_clock -period 10 -waveform {0.000000 5.00000} clk1
>
>
>
> additional PDC constraints imported to Designer:
> assign_global_clock -net {clk2}
> assign_global_clock -net {clk1}
>
>



In your GCF file which you import into Designer:

// To assign net to global buffer
set_global clk2;

// Opposite of above
dont_fix_globals;
set_noglobal clk2;








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