FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-27-2007, 08:43 PM
fl
Guest
 
Posts: n/a
Default What's the difference for VHDL code between simulation and synthesis?

Hi,
The following is from Xilinx "Synthesis and Simulation Design Guide".
Could you give me an example to show their differences? And explain a
little to me? Thank you very much.



You may need to modify your code to successfully synthesize your
design because certain
design constructs that are effective for simulation may not be as
effective for synthesis. The synthesis syntax and code set may differ
slightly from the simulator syntax and code set.
Reply With Quote
  #2 (permalink)  
Old 11-27-2007, 09:41 PM
KJ
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Nov 27, 3:43 pm, fl <[email protected]> wrote:
> Hi,
> The following is from Xilinx "Synthesis and Simulation Design Guide".
> Could you give me an example to show their differences? And explain a
> little to me? Thank you very much.
>
> You may need to modify your code to successfully synthesize your
> design because certain
> design constructs that are effective for simulation may not be as
> effective for synthesis. The synthesis syntax and code set may differ
> slightly from the simulator syntax and code set.


'Differ slightly' is being way too generous. Usually it means more
along the lines of 'not supported at all' for synthesis even though it
is perfectly legitimate code. Some examples and how you would write
the code for simulation are shown below.

1. A delay line (commercially available part from many sources....but
not inside an FPGA typically).
x <= y after 3 ns; -- VHDL representation

2. Division is hard for 2nd graders...not to mention FPGA vendors.
It's not that it can't be synthesized(it can), but it will chew up a
lot of resources and be pretty slow so I guess they figure nobody
would want to do division.
x <= y / z; -- VHDL representation

3. Wait for this event, then that event, then some other thing to
happen
process -- VHDL representation
wait for (This = '1');
wait for rising_edge(That);
wait for (Some_Other_Thing = Happen);
.....
end process;

4. Time? What is that? Without a delay line resource available, a
delay must be synthesized by using counters and clocks to count clock
cycles that roughly mimic the intended delay.
wait for 50.3 ns; -- VHDL representation

There are many others, this is just one tip of the iceberg. In order
to create a design (i.e. to synthesize) something that does each of
the above mentioned things one would make various tradeoffs and would
need to be skilled in basic digital design practices and then could
whip something up that is functionally nearly equivalent to all of the
above.

KJ
Reply With Quote
  #3 (permalink)  
Old 11-27-2007, 10:36 PM
Sylvain Munaut
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Nov 27, 9:43 pm, fl <[email protected]> wrote:
> Hi,
> The following is from Xilinx "Synthesis and Simulation Design Guide".
> Could you give me an example to show their differences? And explain a
> little to me? Thank you very much.
>
> You may need to modify your code to successfully synthesize your
> design because certain
> design constructs that are effective for simulation may not be as
> effective for synthesis. The synthesis syntax and code set may differ
> slightly from the simulator syntax and code set.


There are several possible cases (non exhaustive) :

- Code that's just _not_ syntesizable :

process
begin
wait until reset='0';
wait for 3 ns;
sig <= '1';
end process;

- Code that may / may not be (i.e. if the synthesizer was smart, he
could do it ... but it might not be )

a <= b / c;

- Code that is syntesizable but will most likely result in huge
code ...

e.g. a complete behavioral description of some big stuff but only
using 'simple' behaviors (no unsynthesizable constructs) ...

VHDL is a hardware description language. Meaning that you should _not_
use it to describe what you want the hardware to do. But you should
use it to describe the hardware you want built. It's up to you to find
what hardware to build to do what you want it to do ...


Sylvain

Reply With Quote
  #4 (permalink)  
Old 11-28-2007, 02:59 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

Sylvain Munaut <[email protected]> wrote:

> VHDL is a hardware description language. Meaning that you should _not_
> use it to describe what you want the hardware to do. But you should
> use it to describe the hardware you want built. It's up to you to find
> what hardware to build to do what you want it to do ...


Describing wires explicitly is a very popular style
and works well for synthesis. But it is possible for
me to describe procedurally, how a set of registers
are to be updated, like this:
http://home.comcast.net/~mike_treseler/stack.vhd
And leave it to synthesis to work out the wires, like this:
http://home.comcast.net/~mike_treseler/stack.pdf

-- Mike Treseler
Reply With Quote
  #5 (permalink)  
Old 11-29-2007, 12:28 AM
KJ
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?


"Sylvain Munaut <[email protected]>" <[email protected]> wrote in
message
news:[email protected]m...
> On Nov 27, 9:43 pm, fl <[email protected]> wrote:
> - Code that's just _not_ syntesizable :
>
> process
> begin
> wait until reset='0';
> wait for 3 ns;
> sig <= '1';
> end process;
>

The only reason the above code could be considered 'just _not_ syntesizable'
is because the behaviour of 'sig' prior to getting to where it is assigned
has not been defined and is a design error that one would fix while still in
simulation.

But given that code, if the synthesizer wants to assume that 'sig' defaults
to 1 then it would synthesize to 'sig' always being '1'. If instead it
assumed that 'sig' defaults to '0' then it is again synthesizable with an
inverter and a 3 ns delay line. If market pressure causes the FPGA
suppliers to start adding delay lines to their parts then the above code can
be targeted to one of those devices, if not it can still be implemented with
commercially availabe parts so it is not 'just _not_ syntesizable' it's just
not supported by FPGA software at this time....but there are a whole slew of
things that are not supported, and those are typically
bugs/limitations/whatever with the software that result in web cases to the
support lines when I run across them. The end result of that is they
improve their tool. Things like delay lines would be added as functional
blocks when (if) there is sufficient market demand for that function.

> - Code that may / may not be (i.e. if the synthesizer was smart, he
> could do it ... but it might not be )
>
> a <= b / c;
>

Again, an example not of unsynthesizable code but of perfectly valid and
synthesizable code that a particular supplier may not support for their own
various reasons.

> VHDL is a hardware description language. Meaning that you should _not_
> use it to describe what you want the hardware to do. But you should
> use it to describe the hardware you want built.

I want the tools to figure out the proper bitstream that needs to be loaded
into a part so that a vast array of RAM look up tables, transistors and flip
flops inside that device will implement what I want it to do. In order to
do that I describe functionally what I want the hardware to do, I definitely
do not describe the hardware that I want built (i.e. the look up table
contents, transistor on/off states, etc....and I doubt I'm alone in that
regard).

KJ


Reply With Quote
  #6 (permalink)  
Old 11-30-2007, 03:40 PM
rickman
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Nov 27, 3:43 pm, fl <[email protected]> wrote:
> Hi,
> The following is from Xilinx "Synthesis and Simulation Design Guide".
> Could you give me an example to show their differences? And explain a
> little to me? Thank you very much.
>
> You may need to modify your code to successfully synthesize your
> design because certain
> design constructs that are effective for simulation may not be as
> effective for synthesis. The synthesis syntax and code set may differ
> slightly from the simulator syntax and code set.


I think one thing that others have not pointed out is the fact that an
HDL is just that... a Hardware Description Language. You can use an
HDL to write programs and they will run in a simulator. This is often
done in developing a test bench to drive signals to your device and to
monitor the outputs in simulation. But if you want to write code that
can be synthesized by the compiler, you have to be describing
hardware.

"Describing hardware" means you can only use constructs that the
compiler understands. See the difference? Simulation operates on the
full language. Synthesis only works with a subset that actually
describes hardware.

The examples are far too numerous to list, but here is one. If you
want to use a register, you show it as a process which is scheduled to
run when the clock transitions or the async reset transitions.

Example1: process (SysClk, Reset) begin
if (Reset = '1') then
DataOutReg <= (others => '0');
elsif (rising_edge(SysClk)) then
if (SCFG_CMD = '1') THEN
DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
RTS;
end if;
end if;
end process Example1;

This code "describes" an 8 bit register with SysClk as the clock, and
async reset - Reset and SCFG_CMD as an enable.

To make this unsynthesizable in a way that is sometimes attempted by
newbies...

Example2: process (SysClk, Reset) begin
if (Reset = '1') then
DataOutReg <= (others => '0');
elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
if (SCFG_CMD = '1') THEN
DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
RTS;
end if;
end if;
end process Example2;

You can imagine a register that clocks on both the rising and falling
edge, but you can't build it in an FPGA. It may be useful in
simulation as part of a testbench. For example, you might want to
generated data on both edges of the clock as data returning from a DDR
memory.

Every synthesis tool I have ever used will give you many examples of
valid hardware description code for you to examine. I am not so
familiar with the Altera tools, but I know the Xilinx tools have
provided good examples. Just download one of these free packages and
take it for a test ride. The last time I used the Altera package, the
built in editor was so good, I often forgot whether I was using the
built in editor or my favorite editor. So you shouldn't have too much
trouble learning to use the IDE.

Try the tools and if you have problems, come back and ask about the
problems.
Reply With Quote
  #7 (permalink)  
Old 11-30-2007, 10:15 PM
KJ
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?


"rickman" <[email protected]> wrote in message
news:2c8d9068-fbe9-497d-8d[email protected]
> On Nov 27, 3:43 pm, fl <[email protected]> wrote:
> "Describing hardware" means you can only use constructs that the
> compiler understands. See the difference?

As I pointed out in my first post, what many people refer to as 'not
synthesizable' really means that they can't find a tool that supports the
code as it is written. Something that is 'not synthesizable' can never be
built. Living with the limitations of a particular tool(s) is not the same
thing at all.

> Simulation operates on the
> full language. Synthesis only works with a subset that actually
> describes hardware.
>

Agreed.

> The examples are far too numerous to list, but here is one.

<snip>
> To make this unsynthesizable in a way that is sometimes attempted by
> newbies...
>
> Example2: process (SysClk, Reset) begin
> if (Reset = '1') then
> DataOutReg <= (others => '0');
> elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
> if (SCFG_CMD = '1') THEN
> DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> RTS;
> end if;
> end if;
> end process Example2;
>
> You can imagine a register that clocks on both the rising and falling
> edge, but you can't build it in an FPGA.

But that does not imply that it couldn't be synthesized using two sets of
flip flops whose results get combined. You might not find a synthesis tool
in 2007 that accepts the above code, but that doesn't mean that there won't
be one in 2008 that will. Whether there is such a tool or not depends on
how many users scream to brand A and X that they really need this. It can
be synthesized, just not how you are focusing on how you think it must be
synthesized.

>
> Every synthesis tool I have ever used will give you many examples of
> valid hardware description code for you to examine. I am not so
> familiar with the Altera tools, but I know the Xilinx tools have
> provided good examples. Just download one of these free packages and
> take it for a test ride.

Agreed. Since one needs to get today's job done with tools you have today
you need to understand the limitation of the tools as they are today. I've
submitted dozens of web cases in areas that should be supported but errored
out or produced incorrect results. The tools were updated and improved,
thus changing what was not synthesizable into something that is. Each of
those things were areas where the synthesis tool did not support a language
construct and it should. Bottom line right now for the code I right, I'm
finding Altera way ahead of Xilinx and Synplify so I'm working with X and S
to get their tools improved so that they too can have less stuff that some
would consider to be 'not synthesizable'.

KJ


Reply With Quote
  #8 (permalink)  
Old 12-03-2007, 09:36 AM
Martin Thompson
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?

"KJ" <[email protected]> writes:

> Bottom line right now for the code I right, I'm finding Altera way
> ahead of Xilinx and Synplify so I'm working with X and S to get
> their tools improved so that they too can have less stuff that some
> would consider to be 'not synthesizable'.


Could you give us an example of something Altera can do that Synplify
can't? (I've always "felt" Synplify to be ahead of the vendor-specific
tools, but it sounds like that may have changed :-)

Thanks!
Martin

--
[email protected]
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply With Quote
  #9 (permalink)  
Old 12-03-2007, 05:53 PM
rickman
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Nov 30, 5:15 pm, "KJ" <[email protected]> wrote:
> "rickman" <[email protected]> wrote in message
>
> > The examples are far too numerous to list, but here is one.

> <snip>
> > To make this unsynthesizable in a way that is sometimes attempted by
> > newbies...

>
> > Example2: process (SysClk, Reset) begin
> > if (Reset = '1') then
> > DataOutReg <= (others => '0');
> > elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
> > if (SCFG_CMD = '1') THEN
> > DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > RTS;
> > end if;
> > end if;
> > end process Example2;

>
> > You can imagine a register that clocks on both the rising and falling
> > edge, but you can't build it in an FPGA.

>
> But that does not imply that it couldn't be synthesized using two sets of
> flip flops whose results get combined. You might not find a synthesis tool
> in 2007 that accepts the above code, but that doesn't mean that there won't
> be one in 2008 that will. Whether there is such a tool or not depends on
> how many users scream to brand A and X that they really need this. It can
> be synthesized, just not how you are focusing on how you think it must be
> synthesized.


If you can build the second description, I would like to see that. Do
you know this is possible or are you just speculating? I have never
seen a good example of a register clocked on both edges done in an
FPGA.

Reply With Quote
  #10 (permalink)  
Old 12-03-2007, 06:20 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?

KJ wrote:
> Bottom line right now for the code I right, I'm
> finding Altera way ahead of Xilinx and Synplify so I'm working with X and S
> to get their tools improved so that they too can have less stuff that some
> would consider to be 'not synthesizable'.


Synplify used to have it over quartus on viewers,
but quartus has caught up. As far as synthesis,
it varies with the design, but I would call
A and S comparable for an altera target.
X needs some focus on advanced synthesis.
For example, I wish they would take this one seriously:

http://home.comcast.net/~mike_treseler/proc_demo.vhd
http://home.comcast.net/~mike_tresel...mo_ise_bug.pdf
http://home.comcast.net/~mike_tresel...mo_ise_fix.pdf

It has been hanging fire since ISE 6.1i,
It wouldn't be so bad if I got an error message.
I get synthesis that does not match simulation.

The suggested "solution"
http://www.xilinx.com/support/answers/18452.htm
is to avoid the legal code that causes the problem.
Note that brand A and S and Modelsim get it right.

-- Mike Treseler
Reply With Quote
  #11 (permalink)  
Old 12-03-2007, 07:52 PM
rickman
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Dec 3, 1:20 pm, Mike Treseler <[email protected]> wrote:
> KJ wrote:
> > Bottom line right now for the code I right, I'm
> > finding Altera way ahead of Xilinx and Synplify so I'm working with X and S
> > to get their tools improved so that they too can have less stuff that some
> > would consider to be 'not synthesizable'.

>
> Synplify used to have it over quartus on viewers,
> but quartus has caught up. As far as synthesis,
> it varies with the design, but I would call
> A and S comparable for an altera target.
> X needs some focus on advanced synthesis.
> For example, I wish they would take this one seriously:
>
> http://home.comcast.net/~mike_treseler/proc_demo.vhd
> http://home.comcast.net/~mike_tresel...mo_ise_bug.pdf
> http://home.comcast.net/~mike_tresel...mo_ise_fix.pdf
>
> It has been hanging fire since ISE 6.1i,
> It wouldn't be so bad if I got an error message.
> I get synthesis that does not match simulation.
>
> The suggested "solution"
> http://www.xilinx.com/support/answers/18452.htm
> is to avoid the legal code that causes the problem.
> Note that brand A and S and Modelsim get it right.
>
> -- Mike Treseler


This is an interesting issue. I had to refresh my knowledge of
procedures in VHDL. But I don't understand why you say the Xilinx
solution to the problem is to "avoid the legal code". They are saying
that it will work if you simply pass the variable into the procedure
rather then use it as a global variable. To be honest, I find your
use of procedures for very simple functions inside of a process to be
hard to read. It seems like using parameters instead of a global
might even make the code more readable. Is that something you don't
want to do?
Reply With Quote
  #12 (permalink)  
Old 12-03-2007, 08:16 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

rickman wrote:

> This is an interesting issue. I had to refresh my knowledge of
> procedures in VHDL. But I don't understand why you say the Xilinx
> solution to the problem is to "avoid the legal code". They are saying
> that it will work if you simply pass the variable into the procedure
> rather then use it as a global variable.


The declaration is a regular variable.
The name chosen by the original author is indeed unfortunate.

In vhdl, a "global" would be declared shared.
I am not advocating shared variables or
suggesting that anyone support synthesis for them.

The point is that the variable is in scope
for both procedures, and should not require parameters.
That would be a belt and suspenders.

> To be honest, I find your
> use of procedures for very simple functions inside of a process to be
> hard to read.


The point of my code was to demonstrate a complex problem
in as simple a way as I could, and I guess I fell short of that mark.

The procedure update_regs_fix is the way I would
have coded this example:
_______
procedure update_regs_fix is
begin
if incr = '1' and decr = '0'
then
increment;
elsif incr = '0' and decr = '1'
then
decrement;
end if;
end procedure update_regs_fix;
________

This is very easy for me to read.

> It seems like using parameters instead of a global
> might even make the code more readable.


There is no global variable in either example.
Adding parameters where they
are not needed makes the code *harder*
to read not easier.

-- Mike Treseler
Reply With Quote
  #13 (permalink)  
Old 12-04-2007, 05:35 AM
KJ
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?


"Martin Thompson" <[email protected]> wrote in message
news:[email protected]
> "KJ" <[email protected]> writes:
>
>> Bottom line right now for the code I right, I'm finding Altera way
>> ahead of Xilinx and Synplify so I'm working with X and S to get
>> their tools improved so that they too can have less stuff that some
>> would consider to be 'not synthesizable'.

>
> Could you give us an example of something Altera can do that Synplify
> can't? (I've always "felt" Synplify to be ahead of the vendor-specific
> tools, but it sounds like that may have changed :-)
>


A few years back my general ranking of tools as to adherance to the standard
was Modelsim, Synplify, Quartus. Now a days, I'd put Quartus way ahead of
Synplify with Modelsim still #1 but Quartus a very close 2nd (again, only in
regards to correctly interpreting the code, not anything else). I haven't
played enough with ISE but the little bit that I have seems to put it close
to but a bit behind Synplify. I say that mainly because the first two bugs
I found in ISE were the exact same two bugs that I had with Synplify...but I
think S has fixed them now.

I didn't take too much time to filter these (sorry, getting late) but
hopefully you can get the gist of what isn't working

Example 0: Time is not synthesizable...even as a constant (I 'think' this
is fixed with Synplify now after I reported it a year or so ago....ISE still
doesn't like this but I'm told that they are considering it)

constant PULSE_HIGH_TIME: time := 1 us;
constant CLOCK_PERIOD: time := 10 ns;
signal My_Counter: natural range 0 to (PULSE_HIGH_TIME / CLOCK_PERIOD);



Example 1. This one is somewhat involved but it has to do with when you have
an enumerated type and try to take the 'pos attribute.

Perusing the log file further, it appears that Synplify can produce either a
note or a warning or the above mentioned error when it encounters usage of
an enumerated type. The line that causes the error is

Line 1324: constant CPU_ROUTER_LOW_INDEX_RANGE: natural :=
t_CPU_ROUTER_COMPONENT_CONNECTIONS'pos(t_CPU_ROUTE R_COMPONENT_CONNECTION
S'low);

where 't_CPU_ROUTER_COMPONENT_CONNECTIONS' is defined to be a subtype of
't_CPU_INTERFACES'

Line 1302: subtype t_CPU_ROUTER_COMPONENT_CONNECTIONS is t_CPU_INTERFACES;

and 't_CPU_INTERFACES' is defined to be an enumerated type.

Line 155: type t_CPU_INTERFACES is (rt_Feeder, rt_Track,
rt_SpiIntf,rt_Cam_Cntl, rt_Micr, rt_Trk_Cntl, rt_InkJet, rt_Franker,
rt_Gate,rt_Ports);

The line that causes the error should have returned the position of the
lowest ordered element in the enumerated type. In other words
t_CPU_ROUTER_COMPONENT_CONNECTIONS'pos(t_CPU_ROUTE R_COMPONENT_CONNECTION
S'low)
Since 'rt_Feeder' is the lowermost enumeration, this is equivalent to
t_CPU_ROUTER_COMPONENT_CONNECTIONS'pos(rt_Feeder)
And this should be equal to 0



Example 2: Range of a generic can not be used to define the range of a port

The line of code in question is in one of the outputs of an entity
Line 624: Track_Speed_Select: out natural range
ALLOWABLE_TRACK_SPEEDS'range;

where 'ALLOWABLE_TRACK_SPEEDS' is an input generic for that entity and is
defined on line 519

ALLOWABLE_TRACK_SPEEDS: arr_real := (1.0,1.0);

What Synplify should be doing is taking the range of the input generic and
using that to define the range of the output signal 'Track_Speed_Select'.



Example 3:

@E: CD297
:"C:\Designs\ZFpga_EM1_Syn\HDL\ZFpga_Common\Avl_Le xmark_A640_Ink_Jet_Controller\Avl_Lexmark_A640_Ink _Jet_Controller.vhd":724:3:724:11|Width
mismatch, location has width 32, value 1

The offending line of code is

Line 724: RetVal(i) :=
Convert_Track_Speed_To_Sample_Time(Track_Speed(i), Samples_Per_Second);

But 'RetVal' is defined to be an array of time types
(work.pkg_VHD_Common.arr_time) therefore RetVal(i) (the left side of the
line being reported as an error) is of type 'time'.

The function 'Convert_Track_Speed_To_Sample_Time' is a function that returns
type 'time' as well. The error message indicates that the location has a
width of 32 which is not correct, it has a width of 1.

It should be noted that the use of type 'time' in this design is only for
the purposes of computing other constants that then get used to define
ranges of other signals; I'm not trying to synthesize any signals of type
'time'


Example 4: If you define a record type and have some element that is a
vector you can't use the length of that vector to define the range of an
integer. I think it went something like this....
type t_My_Type is record
....
Some_Field: std_ulogic_vector(7 downto 0);
end record;
....
signal My_Counter: natural range 0 to 2**t_My_Type'Some_Field'length - 1

I reported this one a while back, I'm not sure if it's been fixed in
Synplify or not....ISE has this problem (reported to brand X, they are
taking it under advisement).


KJ


Reply With Quote
  #14 (permalink)  
Old 12-04-2007, 06:02 AM
rickman
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Dec 3, 3:16 pm, Mike Treseler <[email protected]> wrote:
> rickman wrote:
> > This is an interesting issue. I had to refresh my knowledge of
> > procedures in VHDL. But I don't understand why you say the Xilinx
> > solution to the problem is to "avoid the legal code". They are saying
> > that it will work if you simply pass the variable into the procedure
> > rather then use it as a global variable.

>
> The declaration is a regular variable.
> The name chosen by the original author is indeed unfortunate.
>
> In vhdl, a "global" would be declared shared.
> I am not advocating shared variables or
> suggesting that anyone support synthesis for them.
>
> The point is that the variable is in scope
> for both procedures, and should not require parameters.
> That would be a belt and suspenders.


Yes, you are right that this is not a "global" variable. But the
point is that the one way you have it coded does not work with XST.
So why is that a real problem? There are at least two way to code it
correctly. This sort of thing (not supporting all valid code styles)
has plagued HDLs since they were invented.


> > To be honest, I find your
> > use of procedures for very simple functions inside of a process to be
> > hard to read.

>
> The point of my code was to demonstrate a complex problem
> in as simple a way as I could, and I guess I fell short of that mark.
>
> The procedure update_regs_fix is the way I would
> have coded this example:
> _______
> procedure update_regs_fix is
> begin
> if incr = '1' and decr = '0'
> then
> increment;
> elsif incr = '0' and decr = '1'
> then
> decrement;
> end if;
> end procedure update_regs_fix;
> ________
>
> This is very easy for me to read.


Yes, the procedure is easy to read. The procedures increment and
decrement are even easier to read. But in context this just seems to
me to spread the code over many more lines than is needed and does
nothing to *improve* the readability of the code. If you had
procedures that were being shared I could see the point of it. But
this is just breaking the code into modules for the sake of having
modules, in my opinion.

I have coded in Forth and this language encourages the use of many
small routines to facilitate correct coding and debugging. Part of
the goal is to write reusable modules. Here I don't see how the
procedures are easier to code or debug and there is no reuse.


> > It seems like using parameters instead of a global
> > might even make the code more readable.

>
> There is no global variable in either example.
> Adding parameters where they
> are not needed makes the code *harder*
> to read not easier.


I don't agree. If a procedure is modifying a parameter, I easily know
exactly what is happening. If it is modifying a variable that is in a
wider scope, I have to look for the variable and figure out which
scope it currently being used. Even better than parameters would be
to not use procedures for such small snippets of code.

architecture RTL of proc_demo is
begin
p_main : process (clk, rst)
variable count_v : unsigned(data'range);
begin
if rst = '1' then
count_v := (others => '0');
elsif rising_edge(clk) then
if incr = '1' then
count_v := count_v + 1;
end if;
if decr = '1' then
count_v := count_v - 1;
end if;
end if;
data <= std_logic_vector(count_v);
end process;
end RTL;

That is the entire architecture without the procedures, 18 lines vs.
40 for a single example of the procedure version. I can use two
copies of the entire architecture for the two cases and it will still
be smaller than the procedure version which uses 50 lines total for
the two cases. But of course everyone sees things differently. If
very small procedures work for you, go for it.
Reply With Quote
  #15 (permalink)  
Old 12-04-2007, 07:35 AM
Mike Treseler
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

rickman wrote:

> Yes, you are right that this is not a "global" variable. But the
> point is that the one way you have it coded does not work with XST.
> So why is that a real problem?


The fact that XST does not throw an error.

Instead, it silently creates hardware that doesn't sim
anything like the code.

> There are at least two way to code it
> correctly. This sort of thing (not supporting all valid code styles)
> has plagued HDLs since they were invented.


Not supporting every odd version is fine.
Producing a bad netlist is not.

> If you had
> procedures that were being shared I could see the point of it. But
> this is just breaking the code into modules for the sake of having
> modules, in my opinion.


This is a simplified example with one purpose:
to demonstrate the bug to xilinx.

When I write production
code, I use use procedures for duplicated blocks of code.
I do sometimes like to share a variable between
two procedures.
For example, I might want to share an
input register variable between a collect_data
procedure and a readback procedure
that packs in a status bit. It works fine.
If I make a mistake, it shows up in the sim,
just like any other mistake.

-- Mike Treseler
Reply With Quote
  #16 (permalink)  
Old 12-04-2007, 09:38 AM
Martin Thompson
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?

"KJ" <[email protected]> writes:
<a lot!>

Many thanks for that - interesting stuff!

Cheers,
Martin

--
[email protected]
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply With Quote
  #17 (permalink)  
Old 12-04-2007, 12:51 PM
KJ
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?


"rickman" <[email protected]> wrote in message
news:[email protected]...
> On Nov 30, 5:15 pm, "KJ" <[email protected]> wrote:
>> "rickman" <[email protected]> wrote in message
>>
>> > The examples are far too numerous to list, but here is one.

>> <snip>
>> > To make this unsynthesizable in a way that is sometimes attempted by
>> > newbies...

>>
>> > Example2: process (SysClk, Reset) begin
>> > if (Reset = '1') then
>> > DataOutReg <= (others => '0');
>> > elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
>> > if (SCFG_CMD = '1') THEN
>> > DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
>> > RTS;
>> > end if;
>> > end if;
>> > end process Example2;

>>
>> > You can imagine a register that clocks on both the rising and falling
>> > edge, but you can't build it in an FPGA.

>>
>> But that does not imply that it couldn't be synthesized using two sets of
>> flip flops whose results get combined. You might not find a synthesis
>> tool
>> in 2007 that accepts the above code, but that doesn't mean that there
>> won't
>> be one in 2008 that will. Whether there is such a tool or not depends on
>> how many users scream to brand A and X that they really need this. It
>> can
>> be synthesized, just not how you are focusing on how you think it must be
>> synthesized.

>
> If you can build the second description, I would like to see that. Do
> you know this is possible or are you just speculating? I have never
> seen a good example of a register clocked on both edges done in an
> FPGA.
>


Like I said, your description does not imply that it couldn't be synthesized
using two sets of flops suitably combined. See code below for functionally
equivalent code that implements your example 2 but does so in a way that I'm
sure you can see that it can be synthesized. Note, I'm not suggesting that
writing dual edge flop code is good practice or anything, I'm simply saying
that the code that you presented is synthesizable, since it is functionally
equivalent to the code that I list below which clearly is synthesizable.
That implies that your Example 2 code is just not supported by today's
tools, quite possibly due to the lack of any real demand for support for
such coding....but, like I said in the earlier post, 'not supported' is not
the same as 'not synthesizable'.

KJ

Example2a: process (SysClk, Reset) begin
if (Reset = '1') then
DataOutReg_re <= (others => '0');
elsif rising_edge(SysClk) then
if (SCFG_CMD = '1') THEN
DataOutReg_re <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
RTS;
end if;
end if;
end process Example2a;

Example2b: process (SysClk, Reset) begin
if (Reset = '1') then
DataOutReg_fe <= (others => '0');
elsif falling_edge(SysClk) then
if (SCFG_CMD = '1') THEN
DataOutReg_fe <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
RTS;
end if;
end if;
end process Example2b;

DataOutReg <= DataOutReg_re when (SysClk = '1') else DataOutReg_fe;


Reply With Quote
  #18 (permalink)  
Old 12-04-2007, 12:54 PM
KJ
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?


"Martin Thompson" <[email protected]> wrote in message
news:[email protected]
> "KJ" <[email protected]> writes:
> <a lot!>


KJ also copy/pastes to avoid writing <a lot!>. There are of course other
examples but I didn't want to be hammering the suppliers too much in a
public forum.

KJ



Reply With Quote
  #19 (permalink)  
Old 12-04-2007, 03:02 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?

KJ wrote:
> "Martin Thompson" <[email protected]> wrote in message
> news:[email protected]
>> "KJ" <[email protected]> writes:
>> <a lot!>

>
> KJ also copy/pastes to avoid writing <a lot!>. There are of course other
> examples but I didn't want to be hammering the suppliers too much in a
> public forum.


Sometimes they need a nudge.
Thanks for the posting.
I found it informative, and commend you
for taking the time to submit all those bug reports.
Synthesis crosses the newsgroup boundaries,
and I am sometimes conflicted about which groups
are interested in discussing it.


-- Mike Treseler
Reply With Quote
  #20 (permalink)  
Old 12-04-2007, 05:03 PM
rickman
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Dec 4, 7:51 am, "KJ" <[email protected]> wrote:
> "rickman" <[email protected]> wrote in message
>
> news:[email protected]...
>
>
>
> > On Nov 30, 5:15 pm, "KJ" <[email protected]> wrote:
> >> "rickman" <[email protected]> wrote in message

>
> >> > The examples are far too numerous to list, but here is one.
> >> <snip>
> >> > To make this unsynthesizable in a way that is sometimes attempted by
> >> > newbies...

>
> >> > Example2: process (SysClk, Reset) begin
> >> > if (Reset = '1') then
> >> > DataOutReg <= (others => '0');
> >> > elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
> >> > if (SCFG_CMD = '1') THEN
> >> > DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> >> > RTS;
> >> > end if;
> >> > end if;
> >> > end process Example2;

>
> >> > You can imagine a register that clocks on both the rising and falling
> >> > edge, but you can't build it in an FPGA.

>
> >> But that does not imply that it couldn't be synthesized using two sets of
> >> flip flops whose results get combined. You might not find a synthesis
> >> tool
> >> in 2007 that accepts the above code, but that doesn't mean that there
> >> won't
> >> be one in 2008 that will. Whether there is such a tool or not depends on
> >> how many users scream to brand A and X that they really need this. It
> >> can
> >> be synthesized, just not how you are focusing on how you think it must be
> >> synthesized.

>
> > If you can build the second description, I would like to see that. Do
> > you know this is possible or are you just speculating? I have never
> > seen a good example of a register clocked on both edges done in an
> > FPGA.

>
> Like I said, your description does not imply that it couldn't be synthesized
> using two sets of flops suitably combined. See code below for functionally
> equivalent code that implements your example 2 but does so in a way that I'm
> sure you can see that it can be synthesized. Note, I'm not suggesting that
> writing dual edge flop code is good practice or anything, I'm simply saying
> that the code that you presented is synthesizable, since it is functionally
> equivalent to the code that I list below which clearly is synthesizable.
> That implies that your Example 2 code is just not supported by today's
> tools, quite possibly due to the lack of any real demand for support for
> such coding....but, like I said in the earlier post, 'not supported' is not
> the same as 'not synthesizable'.
>
> KJ
>
> Example2a: process (SysClk, Reset) begin
> if (Reset = '1') then
> DataOutReg_re <= (others => '0');
> elsif rising_edge(SysClk) then
> if (SCFG_CMD = '1') THEN
> DataOutReg_re <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> RTS;
> end if;
> end if;
> end process Example2a;
>
> Example2b: process (SysClk, Reset) begin
> if (Reset = '1') then
> DataOutReg_fe <= (others => '0');
> elsif falling_edge(SysClk) then
> if (SCFG_CMD = '1') THEN
> DataOutReg_fe <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> RTS;
> end if;
> end if;
> end process Example2b;
>
> DataOutReg <= DataOutReg_re when (SysClk = '1') else DataOutReg_fe;


I am not sure you are correct in that the two circuits are
equivalent. I was thinking about how such a circuit would not work in
a practical sense, although logically it is the same as the one I
wrote. So from a synthesis standpoint, this circuit could be
synthesized. However, it would likely not work as intended since it
depends too much on controlling delays. So I see your point, but I
disagree that the two circuits are the same.

I don't argue that "not supported" is the same as "not
synthesizable". But I think there is a very small set of useful
designs that are synthesizable but not supported by most vendors.
Reply With Quote
  #21 (permalink)  
Old 12-04-2007, 11:21 PM
glen herrmannsfeldt
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation and synthesis?

KJ wrote:
(snip)

> As I pointed out in my first post, what many people refer to as 'not
> synthesizable' really means that they can't find a tool that supports the
> code as it is written. Something that is 'not synthesizable' can never be
> built. Living with the limitations of a particular tool(s) is not the same
> thing at all.


>>Simulation operates on the
>>full language. Synthesis only works with a subset that actually
>>describes hardware.


> Agreed.


Absolute delays will likely never be synthesizable, for example.

>>The examples are far too numerous to list, but here is one.


(snip)

>>You can imagine a register that clocks on both the rising and falling
>>edge, but you can't build it in an FPGA.


> But that does not imply that it couldn't be synthesized using two sets of
> flip flops whose results get combined. You might not find a synthesis tool
> in 2007 that accepts the above code, but that doesn't mean that there won't
> be one in 2008 that will. Whether there is such a tool or not depends on
> how many users scream to brand A and X that they really need this. It can
> be synthesized, just not how you are focusing on how you think it must be
> synthesized.


On the other hand, if it can be done why not do it as a module.
(That would be verilog, but VHDL has something similar.)

Most don't synthesize a variable divide, but usually one would want
to use a module, anyway. (For example, to do a pipelined divide.)

Unless the hardware implemented a two edge FF, I don't think
one should synthesize one. It is likely to be slow, exactly what
you don't want in a two edge FF.

-- glen

Reply With Quote
  #22 (permalink)  
Old 12-05-2007, 01:57 PM
Andy
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Dec 4, 1:35 am, Mike Treseler <[email protected]> wrote:
> rickman wrote:
> > Yes, you are right that this is not a "global" variable. But the
> > point is that the one way you have it coded does not work with XST.
> > So why is that a real problem?

>
> The fact that XST does not throw an error.
>
> Instead, it silently creates hardware that doesn't sim
> anything like the code.
>
> > There are at least two way to code it
> > correctly. This sort of thing (not supporting all valid code styles)
> > has plagued HDLs since they were invented.

>
> Not supporting every odd version is fine.
> Producing a bad netlist is not.
>
> > If you had
> > procedures that were being shared I could see the point of it. But
> > this is just breaking the code into modules for the sake of having
> > modules, in my opinion.

>
> This is a simplified example with one purpose:
> to demonstrate the bug to xilinx.
>
> When I write production
> code, I use use procedures for duplicated blocks of code.
> I do sometimes like to share a variable between
> two procedures.
> For example, I might want to share an
> input register variable between a collect_data
> procedure and a readback procedure
> that packs in a status bit. It works fine.
> If I make a mistake, it shows up in the sim,
> just like any other mistake.
>
> -- Mike Treseler


I agree wholeheartedly, Xilinx should not produce incorrect results,
without an error message. Either do it right, or don't do it (stop
with error).

Andy
Reply With Quote
  #23 (permalink)  
Old 12-05-2007, 02:17 PM
Andy
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Dec 4, 11:03 am, rickman <[email protected]> wrote:
> On Dec 4, 7:51 am, "KJ" <[email protected]> wrote:
>
>
>
> > "rickman" <[email protected]> wrote in message

>
> >news:[email protected]...

>
> > > On Nov 30, 5:15 pm, "KJ" <[email protected]> wrote:
> > >> "rickman" <[email protected]> wrote in message

>
> > >> > The examples are far too numerous to list, but here is one.
> > >> <snip>
> > >> > To make this unsynthesizable in a way that is sometimes attempted by
> > >> > newbies...

>
> > >> > Example2: process (SysClk, Reset) begin
> > >> > if (Reset = '1') then
> > >> > DataOutReg <= (others => '0');
> > >> > elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
> > >> > if (SCFG_CMD = '1') THEN
> > >> > DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > >> > RTS;
> > >> > end if;
> > >> > end if;
> > >> > end process Example2;

>
> > >> > You can imagine a register that clocks on both the rising and falling
> > >> > edge, but you can't build it in an FPGA.

>
> > >> But that does not imply that it couldn't be synthesized using two sets of
> > >> flip flops whose results get combined. You might not find a synthesis
> > >> tool
> > >> in 2007 that accepts the above code, but that doesn't mean that there
> > >> won't
> > >> be one in 2008 that will. Whether there is such a tool or not depends on
> > >> how many users scream to brand A and X that they really need this. It
> > >> can
> > >> be synthesized, just not how you are focusing on how you think it must be
> > >> synthesized.

>
> > > If you can build the second description, I would like to see that. Do
> > > you know this is possible or are you just speculating? I have never
> > > seen a good example of a register clocked on both edges done in an
> > > FPGA.

>
> > Like I said, your description does not imply that it couldn't be synthesized
> > using two sets of flops suitably combined. See code below for functionally
> > equivalent code that implements your example 2 but does so in a way that I'm
> > sure you can see that it can be synthesized. Note, I'm not suggesting that
> > writing dual edge flop code is good practice or anything, I'm simply saying
> > that the code that you presented is synthesizable, since it is functionally
> > equivalent to the code that I list below which clearly is synthesizable.
> > That implies that your Example 2 code is just not supported by today's
> > tools, quite possibly due to the lack of any real demand for support for
> > such coding....but, like I said in the earlier post, 'not supported' is not
> > the same as 'not synthesizable'.

>
> > KJ

>
> > Example2a: process (SysClk, Reset) begin
> > if (Reset = '1') then
> > DataOutReg_re <= (others => '0');
> > elsif rising_edge(SysClk) then
> > if (SCFG_CMD = '1') THEN
> > DataOutReg_re <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > RTS;
> > end if;
> > end if;
> > end process Example2a;

>
> > Example2b: process (SysClk, Reset) begin
> > if (Reset = '1') then
> > DataOutReg_fe <= (others => '0');
> > elsif falling_edge(SysClk) then
> > if (SCFG_CMD = '1') THEN
> > DataOutReg_fe <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > RTS;
> > end if;
> > end if;
> > end process Example2b;

>
> > DataOutReg <= DataOutReg_re when (SysClk = '1') else DataOutReg_fe;

>
> I am not sure you are correct in that the two circuits are
> equivalent. I was thinking about how such a circuit would not work in
> a practical sense, although logically it is the same as the one I
> wrote. So from a synthesis standpoint, this circuit could be
> synthesized. However, it would likely not work as intended since it
> depends too much on controlling delays. So I see your point, but I
> disagree that the two circuits are the same.
>
> I don't argue that "not supported" is the same as "not
> synthesizable". But I think there is a very small set of useful
> designs that are synthesizable but not supported by most vendors.


The following double edge flop implementation avoids potential
glitches on the output (after all, it is supposed to act like a
register). Not all synthesis tools support the single process style,
but it can easily be split into two clocked processes and a concurrent
assignment.

process (clk, rst) is
variable qr,qf : std_logic;
begin
if rst = '1' then
qr := '0';
qf := '0';
elsif rising_edge(clk) then
qr := d xor qf;
elsif falling_edge(clk) then
qf := d xor qr;
end if;
q <= qr xor qf; -- combinatorial xor of registered qr,qf
end process;

This description also illustrates a way to have combinatorial logic on
the output of registers, within a clocked process. That is a very
useful feature that is not supported by all tools. It also allows for
the exportation via signals (or output ports) from local variables
(registered values thereof), without creating a duplicate register
that is then (usually) optimized out.

Andy
Reply With Quote
  #24 (permalink)  
Old 12-05-2007, 04:28 PM
rickman
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Dec 5, 9:17 am, Andy <[email protected]> wrote:
> On Dec 4, 11:03 am, rickman <[email protected]> wrote:
>
>
>
> > On Dec 4, 7:51 am, "KJ" <[email protected]> wrote:

>
> > > "rickman" <[email protected]> wrote in message

>
> > >news:[email protected]...

>
> > > > On Nov 30, 5:15 pm, "KJ" <[email protected]> wrote:
> > > >> "rickman" <[email protected]> wrote in message

>
> > > >> > The examples are far too numerous to list, but here is one.
> > > >> <snip>
> > > >> > To make this unsynthesizable in a way that is sometimes attempted by
> > > >> > newbies...

>
> > > >> > Example2: process (SysClk, Reset) begin
> > > >> > if (Reset = '1') then
> > > >> > DataOutReg <= (others => '0');
> > > >> > elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
> > > >> > if (SCFG_CMD = '1') THEN
> > > >> > DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > > >> > RTS;
> > > >> > end if;
> > > >> > end if;
> > > >> > end process Example2;

>
> > > >> > You can imagine a register that clocks on both the rising and falling
> > > >> > edge, but you can't build it in an FPGA.

>
> > > >> But that does not imply that it couldn't be synthesized using two sets of
> > > >> flip flops whose results get combined. You might not find a synthesis
> > > >> tool
> > > >> in 2007 that accepts the above code, but that doesn't mean that there
> > > >> won't
> > > >> be one in 2008 that will. Whether there is such a tool or not depends on
> > > >> how many users scream to brand A and X that they really need this. It
> > > >> can
> > > >> be synthesized, just not how you are focusing on how you think it must be
> > > >> synthesized.

>
> > > > If you can build the second description, I would like to see that. Do
> > > > you know this is possible or are you just speculating? I have never
> > > > seen a good example of a register clocked on both edges done in an
> > > > FPGA.

>
> > > Like I said, your description does not imply that it couldn't be synthesized
> > > using two sets of flops suitably combined. See code below for functionally
> > > equivalent code that implements your example 2 but does so in a way that I'm
> > > sure you can see that it can be synthesized. Note, I'm not suggesting that
> > > writing dual edge flop code is good practice or anything, I'm simply saying
> > > that the code that you presented is synthesizable, since it is functionally
> > > equivalent to the code that I list below which clearly is synthesizable.
> > > That implies that your Example 2 code is just not supported by today's
> > > tools, quite possibly due to the lack of any real demand for support for
> > > such coding....but, like I said in the earlier post, 'not supported' is not
> > > the same as 'not synthesizable'.

>
> > > KJ

>
> > > Example2a: process (SysClk, Reset) begin
> > > if (Reset = '1') then
> > > DataOutReg_re <= (others => '0');
> > > elsif rising_edge(SysClk) then
> > > if (SCFG_CMD = '1') THEN
> > > DataOutReg_re <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > > RTS;
> > > end if;
> > > end if;
> > > end process Example2a;

>
> > > Example2b: process (SysClk, Reset) begin
> > > if (Reset = '1') then
> > > DataOutReg_fe <= (others => '0');
> > > elsif falling_edge(SysClk) then
> > > if (SCFG_CMD = '1') THEN
> > > DataOutReg_fe <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
> > > RTS;
> > > end if;
> > > end if;
> > > end process Example2b;

>
> > > DataOutReg <= DataOutReg_re when (SysClk = '1') else DataOutReg_fe;

>
> > I am not sure you are correct in that the two circuits are
> > equivalent. I was thinking about how such a circuit would not work in
> > a practical sense, although logically it is the same as the one I
> > wrote. So from a synthesis standpoint, this circuit could be
> > synthesized. However, it would likely not work as intended since it
> > depends too much on controlling delays. So I see your point, but I
> > disagree that the two circuits are the same.

>
> > I don't argue that "not supported" is the same as "not
> > synthesizable". But I think there is a very small set of useful
> > designs that are synthesizable but not supported by most vendors.

>
> The following double edge flop implementation avoids potential
> glitches on the output (after all, it is supposed to act like a
> register). Not all synthesis tools support the single process style,
> but it can easily be split into two clocked processes and a concurrent
> assignment.
>
> process (clk, rst) is
> variable qr,qf : std_logic;
> begin
> if rst = '1' then
> qr := '0';
> qf := '0';
> elsif rising_edge(clk) then
> qr := d xor qf;
> elsif falling_edge(clk) then
> qf := d xor qr;
> end if;
> q <= qr xor qf; -- combinatorial xor of registered qr,qf
> end process;
>
> This description also illustrates a way to have combinatorial logic on
> the output of registers, within a clocked process. That is a very
> useful feature that is not supported by all tools. It also allows for
> the exportation via signals (or output ports) from local variables
> (registered values thereof), without creating a duplicate register
> that is then (usually) optimized out.


The only trouble is that this is not at all equivalent to the code I
wrote. This code is describing two registers with two separate inputs
and two separate outputs that are then XORed together. How is this
like a register that is clocked on both edges of the clock?

Reply With Quote
  #25 (permalink)  
Old 12-05-2007, 04:33 PM
rickman
Guest
 
Posts: n/a
Default Re: What's the difference for VHDL code between simulation andsynthesis?

On Dec 4, 2:35 am, Mike Treseler <[email protected]> wrote:
> rickman wrote:
> > Yes, you are right that this is not a "global" variable. But the
> > point is that the one way you have it coded does not work with XST.
> > So why is that a real problem?

>
> The fact that XST does not throw an error.
>
> Instead, it silently creates hardware that doesn't sim
> anything like the code.


Yes, I was forgetting that "little" issue.


> > There are at least two way to code it
> > correctly. This sort of thing (not supporting all valid code styles)
> > has plagued HDLs since they were invented.

>
> Not supporting every odd version is fine.
> Producing a bad netlist is not.


I agree. This is the sort of thing that is very hard to find in a
design once it gets past your simulation and fails on the real chip.
I suppose it would fail in a post route simulation, no?


> > If you had
> > procedures that were being shared I could see the point of it. But
> > this is just breaking the code into modules for the sake of having
> > modules, in my opinion.

>
> This is a simplified example with one purpose:
> to demonstrate the bug to xilinx.


Yes, I agree with you and I see that my concerns would not valid.


> When I write production
> code, I use use procedures for duplicated blocks of code.
> I do sometimes like to share a variable between
> two procedures.
> For example, I might want to share an
> input register variable between a collect_data
> procedure and a readback procedure
> that packs in a status bit. It works fine.
> If I make a mistake, it shows up in the sim,
> just like any other mistake.
>
> -- Mike Treseler


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
the synthesis difference [email protected] Verilog 2 05-19-2008 02:08 AM
Is there a Single simulation n synthesis code for Flip-Flop? Viji Verilog 3 09-23-2006 09:29 AM
Difference between simulation types Preben Holm FPGA 3 03-30-2005 02:13 AM
What is the difference between task and function in synthesis? Lee Verilog 0 06-09-2004 11:15 PM


All times are GMT +1. The time now is 09:05 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved