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Old 04-14-2006, 03:51 PM
kelvins
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Default what wrong of this counter ?

Hi all,
i have a problem, the code as below, the all condition
signals(excludes rst_n)
is generated by posedge clk_in. I have run in simulation the counter
"count" is normal.
the new "count" is generated by posedge clk_in. but when I use FPGA
emulation
and observe the new "count" in sometime is generated by negedge
clk_in. what happen
to this situation? it cannot same as simulation result.
I am using Quartus 5.0 for compiling and fitting, the timing report is
OK.
Hope someone could give me some suggestion to this situation, thanks a
lot.

################################################## ##########
always @(negedge rst_n or posedge clk_in)
if ( !rst_n ) begin
count <=4'b0;
end else begin
if ( inst_en ) begin
count <=4'b0;
end else begin
if ( op_state ) begin
if( count==`OP_CNT ) count <=4'b0;
else if ( !c_sel ) count <= count + 1;
end else if (byte_state) begin
if( count==`BYTE_CNT ) count <=4'b0;
else if ( !c_sel ) count <= count + 1;
end else if ( addr_state ) begin
if( count==`ADDR_CNT ) count <=4'b0;
else if ( !c_sel ) count <= count + 1;
end else if ( data_state ) begin
if ( inst==`AA_wr || inst==op_program ) begin
if( count==`BYTE_CNT ) count <=4'b0;
else if ( !c_sel && hold_wr ) count <= count + 1;
end else begin
if( count==`BYTE_CNT ) count <=4'b0;
else if ( !c_sel && hold_rd ) count <= count + 1;
end
end
end
end
################################################## ############

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  #2 (permalink)  
Old 04-16-2006, 04:26 PM
kelvins
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Posts: n/a
Default Re: what wrong of this counter ?

I found this was clock source issue, the PLL for mmu clock (on the FPGA
board) would appeared clock glitch in low frequency (12 MHz~ 30MHz) .
As I used a simple crcuit for verifying as below,
#############################################
always @(negedge rst_n or posedge clk_in)
if ( !rst_n ) begin
toggle_signal <=1'b0;
end else begin
toggle_signal <=~ toggle_signal;
end
#############################################
I found the toggle_signal also changed in falling edge, and check the
pll source in logic
analyzer, found there was glitch occured.

Share some experience with you all.

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  #3 (permalink)  
Old 04-16-2006, 07:26 PM
Peter Alfke
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Default Re: what wrong of this counter ?

There is a "dirty trick" that allows you to live with a glitch on the
falling clock edge, when you really want to trigger only on the rising
clock edge:
Take the clock input, invert it, and use it then as Count Enable on
your counter.
That disbles the counter while the clock is High, plus a little bit
beyond, and thus masks the double transition of the falling clock edge.
You may have to add some delay to the Count Enable input.

This is a BandAid, the proper solution is to terminate the clock line,
so that you do not get the glitch.
Peter Alfke, Xilinx Applictions. Occasionally also helping an Altera
user in distress...

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  #4 (permalink)  
Old 04-17-2006, 04:58 PM
kelvins
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Default Re: what wrong of this counter ?

Hi, Peter,
Thank for your suggestion.
But I have two questions now:
(1) if i want to "filter" the clock source for generating a new clear
clock,
how can i do ?
(2) you mentioned "add some delay to ...", can i add use LCELL()
delay cell ?
And if i use DC synthesis, how can i do and how can i guarantee
delay is proper ?


thanks

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  #5 (permalink)  
Old 04-17-2006, 05:54 PM
Peter Alfke
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Default Re: what wrong of this counter ?

I offered a "BandAid", not a cure.
Just invert the clock and use this inverted clock as CE.
This does not eliminate the glitch, but it makes sure that the counter
does not react to it.
Maybe you do not need any extra delay...
Peter Alfke

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