Well, if you have the tools, why don't you have a look at the results?
Just use the Floorplanner or the
FPGA Editor.
If nothing helps, try a more recent version. You may wish to have a look
at the xilinx home page.
BR Chris
Kload wrote:
> Hi all,
>
> Lets assume I'm using a Xilinx Virtex device and I have a VHDL design
> that includes the following
>
> a<=b+c;
>
> Will the design tools (I happen to be using Foundation 2.1i) infer a
> "simple" adder or will the tools automatically infer an adder that uses
> the dedicated carry look ahead logic?? Will that logic be placed
> appropriately (i.e. like the ACC and ADD standard components that use
> the RLOC constraint)?
>
> Thanks for your help.
>