FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 02-12-2007, 03:42 AM
Gavin Melville
Guest
 
Posts: n/a
Default Weird problem with WP 9.1sp1 and XC95144XL

Hi,

I've got a really strange problem with a XC95144XL. It's a simple
design, all schematic based, and the device is not behaving -- but
only sort of. Pins that are unused are turning into weak outputs,
some outputs work, and other don't (they may be high or low). I have
data buses with 6 out of 8 pins working. Change something and
recompile, reload and the results will be different eg. same data bus
but now 5 pins work correctly and 3 are high or low. Most of the
internal logic seems to be working OK -- this only seems to affect IO
pins.

I've checked:

All pins (this is a TQ100 if that matters), including VCC/GND.
A few pins ar "fast", most are not, and the 3.3 V supply looks fine.
The download from a Parallel IV cable is verifyable, and repeated
downloads work (or fail to work) the same.
All the Fitter / Placer warnings make sense.
The equations in the reports are all correct.

If I add some unneeded logic ie. add a counter, clock it and feed one
output to an unused pin then the symptoms change.

Yes -- I do have it setup for the correct device.

Any bright ideas (or even some really silly ones)

While I hopefully wait for those I'm downloading 8.2 again.....


--

TIA,
Gavin Melville
[email protected]
Reply With Quote
  #2 (permalink)  
Old 02-12-2007, 05:09 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: Weird problem with WP 9.1sp1 and XC95144XL

Gavin Melville wrote:
> Hi,
>
> I've got a really strange problem with a XC95144XL. It's a simple
> design, all schematic based, and the device is not behaving -- but
> only sort of. Pins that are unused are turning into weak outputs,
> some outputs work, and other don't (they may be high or low). I have
> data buses with 6 out of 8 pins working. Change something and
> recompile, reload and the results will be different eg. same data bus
> but now 5 pins work correctly and 3 are high or low. Most of the
> internal logic seems to be working OK -- this only seems to affect IO
> pins.
>
> I've checked:
>
> All pins (this is a TQ100 if that matters), including VCC/GND.
> A few pins ar "fast", most are not, and the 3.3 V supply looks fine.
> The download from a Parallel IV cable is verifyable, and repeated
> downloads work (or fail to work) the same.
> All the Fitter / Placer warnings make sense.
> The equations in the reports are all correct.
>
> If I add some unneeded logic ie. add a counter, clock it and feed one
> output to an unused pin then the symptoms change.
>
> Yes -- I do have it setup for the correct device.
>
> Any bright ideas (or even some really silly ones)


If you have an older design iteration archived, you could download that
to check all the hardware is OK ?

You have checked the fitter pin-report to make sure it is not
moving pins about ?

There have been other postings here about Xilinx CPLD flows,
which suggest their PLD regression testing is, shall we say, "Casual".

-jg


Reply With Quote
  #3 (permalink)  
Old 02-12-2007, 12:23 PM
Benjamin Todd
Guest
 
Posts: n/a
Default Re: Weird problem with WP 9.1sp1 and XC95144XL

I remember in one of the previous releases of ISE where the JEDEC file
creator was completely wrong for the XC9500. It inverted all the outputs.
Makes CPLD design very challenging when you start questioning the tools not
the design.
Ben

"Jim Granville" <[email protected]> wrote in message
news:[email protected]
> Gavin Melville wrote:
>> Hi,
>>
>> I've got a really strange problem with a XC95144XL. It's a simple
>> design, all schematic based, and the device is not behaving -- but
>> only sort of. Pins that are unused are turning into weak outputs,
>> some outputs work, and other don't (they may be high or low). I have
>> data buses with 6 out of 8 pins working. Change something and
>> recompile, reload and the results will be different eg. same data bus
>> but now 5 pins work correctly and 3 are high or low. Most of the
>> internal logic seems to be working OK -- this only seems to affect IO
>> pins.
>>
>> I've checked:
>>
>> All pins (this is a TQ100 if that matters), including VCC/GND.
>> A few pins ar "fast", most are not, and the 3.3 V supply looks fine.
>> The download from a Parallel IV cable is verifyable, and repeated
>> downloads work (or fail to work) the same.
>> All the Fitter / Placer warnings make sense.
>> The equations in the reports are all correct.
>>
>> If I add some unneeded logic ie. add a counter, clock it and feed one
>> output to an unused pin then the symptoms change.
>>
>> Yes -- I do have it setup for the correct device.
>>
>> Any bright ideas (or even some really silly ones)

>
> If you have an older design iteration archived, you could download that to
> check all the hardware is OK ?
>
> You have checked the fitter pin-report to make sure it is not
> moving pins about ?
>
> There have been other postings here about Xilinx CPLD flows,
> which suggest their PLD regression testing is, shall we say, "Casual".
>
> -jg
>
>



Reply With Quote
  #4 (permalink)  
Old 02-12-2007, 01:48 PM
Guest
 
Posts: n/a
Default Re: Weird problem with WP 9.1sp1 and XC95144XL

On Feb 12, 5:09 pm, Jim Granville <[email protected]>
wrote:

> If you have an older design iteration archived, you could download that
> to check all the hardware is OK ?


Not for that device -- the design got too big. The smaller one was
done with 8.2.03, and I've downloaded that now -- I'll try it
tomorrow.

> You have checked the fitter pin-report to make sure it is not
> moving pins about ?


Yes I have. In some ways it's stranger than that -- take two pins
that should be a CPU databus (but are actually permanently low) -- if
I ground (internally) either one, the other works, however if I pull
either to VCC the other stays grounded.

> There have been other postings here about Xilinx CPLD flows,
> which suggest their PLD regression testing is, shall we say, "Casual".


As a user of about 10 different versions from DOS Viewlogic forward
I've never noticed that before. I've always found the software to be
rock solid, well tested and clearly documented ;-)

Reply With Quote
  #5 (permalink)  
Old 02-12-2007, 02:32 PM
Andreas Ehliar
Guest
 
Posts: n/a
Default Re: Weird problem with WP 9.1sp1 and XC95144XL

On 2007-02-12, [email protected] <[email protected]> wrote:
> Yes I have. In some ways it's stranger than that -- take two pins
> that should be a CPU databus (but are actually permanently low) -- if
> I ground (internally) either one, the other works, however if I pull
> either to VCC the other stays grounded.
>


The problem I had with a 9536 was "solved" by setting FSM extraction to
no in the Xilinx tool. I also got a report that enabling WYSIWYG mode
helped but I did not verify that myself since I had already gotten the
design to work.

/Andreas
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Weird 2D-array issue Michael Meeuwisse Verilog 8 07-01-2008 09:54 PM
Weird timing failure JL FPGA 2 07-06-2006 09:09 AM
Weird problem in Xilinx WebPack ISE PACE 7.1SP4 [email protected] FPGA 0 10-03-2005 06:07 AM
weird problem printing Xilinx state machine starfire FPGA 1 01-08-2005 09:25 PM
Weird Compile Error ~~ VerilogMan ~~ Verilog 11 10-13-2004 11:51 PM


All times are GMT +1. The time now is 06:14 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved