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Old 10-31-2007, 08:08 AM
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Default Weird behavior : Altera DE2, C++, For loops, SRAM

So I've implemented a NIOS II board using the SOPC builder. I ran out
of on-chip memory so I went off-chip to the DE2's SRAM. Suddenly my
programs stopped working and the for loops has an unusual behavior.

It'll go outside of the for loop..

for instance:
-----------------
//assume variables defined

For (i = 0; i < 3999999; i++)
{
IOWR_8DIRECT(memory_base, i, 0xff); //Writes all 1's to SDRAM
}

printf("Finished...\n");

.... more code...

------------------

What ends up happening is that the loop will run with the
printf("Finished...") statement and repeat for the duration of the
loop.

Output:
Finished...
Finished...
Finished...
..
..
You get the idea... I didn't let it loop 4 million times you see what
happened.


This ONLY happens when I use the SRAM. If I use the SDRAM or the on-
chip memory it works fine.

Any one run into this problem?

Thanks,
el

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Old 11-05-2007, 03:31 PM
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Default Re: Weird behavior : Altera DE2, C++, For loops, SRAM

On Oct 31, 2:08 am, [email protected] wrote:
> SoI'veimplementedaNIOSIIboardusingtheSOPCbuilder. I ran out
> of on-chip memorysoI went off-chip to the DE2's SRAM. Suddenly my
> programs stopped working and the for loops has an unusual behavior.
>
> It'll go outside of the for loop..
>
> for instance:
> -----------------
> //assume variables defined
>
> For (i = 0; i < 3999999; i++)
> {
> IOWR_8DIRECT(memory_base, i, 0xff); //Writes all 1's to SDRAM
>
> }
>
> printf("Finished...\n");
>
> ... more code...
>
> ------------------
>
> What ends up happening is that the loop will run with the
> printf("Finished...") statement and repeat for the duration of the
> loop.
>
> Output:
> Finished...
> Finished...
> Finished...
> .
> .
> You get the idea... I didn't let it loop 4 million times you see what
> happened.
>
> This ONLY happens when I use the SRAM. If I use the SDRAM or the on-
> chip memory it works fine.
>
> Any one run into this problem?
>
> Thanks,
> el


There are no reported problems with the DE2 SRAM behavior in the field
(from many thousands of users), so at least the problem you are seeing
is not common. One possible explanation could be timing constraints.
As I'm sure you know, it is a good idea to include proper Tco and Tsu
constraints when dealing with any device outside of the FPGA. We have
previously seen a similar error for one customer, and the error was
fixed when they added I/O timing constraints for the SRAM.

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