FPGA Central

Hello All,

I have got a warning (below) during implementation of my design which
uses 50 MHz clock on Spartan 3E 1600E Microblaze Development Kit. What
could be a reason for this warning and how it could be fixed?

WARNING:iMPACT:2257-Startup clock has been changed to 'JtagClk' in the
bitstream stored in memory, but the original bitstream file remains
unchanged.

On Jan 8, 2:19 pm, Vagant <[email protected]> wrote:
> Hello All,
>
> I have got a warning (below) during implementation of my design which
> uses 50 MHz clock on Spartan 3E 1600E Microblaze Development Kit. What
> could be a reason for this warning and how it could be fixed?
>
> WARNING:iMPACT:2257-Startup clock has been changed to 'JtagClk' in the
> bitstream stored in memory, but the original bitstream file remains
> unchanged.

You do not need to fix anything unless you just want to make the
warning go away.

This just means that bitgen was told to generate the bitfile with the
startup clock set to CCLK. Since you are downloading with a JTAG
cable, Impact automatically modified the bitfile before downloading it
for you. In EDK you can edit the project_dir/etc/bitgen.ut file in
your project to change the startup clock option.

If you plan on putting your bitfile into what ever config memory you
have on the card, I would just leave the startup clock set to CCLK
like it is now. Impact will work fine with it that way, but changing
it to use the JtagClk would cause you problems if you forget to change
it back before creating a bitfile for the config memory.

Regards,

John McCaskill
www.FasterTechnology.com

On Jan 8, 3:19 pm, Vagant <[email protected]> wrote:
> Hello All,
>
> I have got a warning (below) during implementation of my design which
> uses 50 MHz clock on Spartan 3E 1600E Microblaze Development Kit. What
> could be a reason for this warning and how it could be fixed?
>
> WARNING:iMPACT:2257-Startup clock has been changed to 'JtagClk' in the
> bitstream stored in memory, but the original bitstream file remains
> unchanged.

This is talking about the configuration startup clock, not the 50 MHz
system clock of your running design. If your bitstream settings are
default, your CCLK will normally be used to start up the FPGA after
configuration. When using iMPACT in JTAG mode, this clock is not
available, so iMPACT changes it for you to use the JTAG TCK signal
instead. This is the normal behavior, and you don't need to worry
about it. Additional information on configuration is available in the
Spartan 3 Generation Configuration User Guide, ug332.pdf, available
on the Xilinx website.

Thank you very much for replies!