FPGA Central

I did some search on the topic and the results were quite
disappointing, though
I would expect something like that should exist:

I am working on a theoretical, combinational problem.
My software implementation runs for hours for small problems.
The main operation is a small table lookup, some additions, etc.
However, I use some data structures for reuse of previously computed
results.
In my SW implementation these are C++ Standard Template Library
instances,
for instance a set<vector<unsigned short> >, so essentially a hash
table.
Another structure is a vector<vector<short int* > >, where the
innermost array grows up to 10 or 12 elements,
and the outer structures to 30 and several hundrets resp. The problem
offers more parallelism than one could
wish for and the updates to the data structures are moderately
frequent.
Too frequent however, to do it in SW on a processor.
I even have a Spartan-3 board with external memory, this would be fine
for running the problem on.

However, I do not want to implement these data structures from
scratch, which probably would require memory management, caching etc.
I think it should be possible to make a circuit generator (similar to
the BRASS one)
where you feed your required data structures in, adding parameters,
like the expected size, update rate etc.
and get a circuit out, which will implement them. Similar to the C++
runtime library it would share the memory ressources, use a memory
manager but allow parallel requests. In my case I would like to have a
high number of ports for the addition to the hash table mentioned
first.
Seems like a great project for a thesis or a class.

Does someone know, where this has been done?

Thanks,
Andreas