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  #1 (permalink)  
Old 12-30-2003, 07:01 PM
ed
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Default virtex-II problems

I'm building a multi-channel frequency synthesizer in a Xilinx
XC2V6000-6 ES. I have verified a one and two channel build, but when I
move to four channels the design stops working (slice usage goes from
12% with one channel to 50% with four). It looks as if the design is
not clocking (all registers are returning '0' and there is no response
to inputs). The only differences between the builds are the number of
times the "channel module" is generated, a modification to a priority
LUT, and a different adder to sum all the outputs of each "channel
module". All timing constraints are met.

I have tried a number of things: Different reset logic on the DCMs,
removing the DCMs altogether and just using the IBUFGs and BUFGs,
using a non-ES version of the chip, etc. Nothing seems to work. Does
anyone have any ideas?

Thanks

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where
"xy" = "ed.agunos"
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  #2 (permalink)  
Old 12-30-2003, 07:14 PM
Mark Schellhorn
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Default Re: virtex-II problems

Try looking in the Answers Database for ES "anomalies" that might be biting you.
I searched on XC2V6000-6 ES and came up with a bunch of potential hits like this
one regarding quadrant restrictions for IBUFG routing:

http://support.xilinx.com/xlnx/xil_a...PagePath=11756

There are other ES errata that apply to DCM usage, but you say that you've
already tried running without DCMs.

Mark


ed wrote:
> I'm building a multi-channel frequency synthesizer in a Xilinx
> XC2V6000-6 ES. I have verified a one and two channel build, but when I
> move to four channels the design stops working (slice usage goes from
> 12% with one channel to 50% with four). It looks as if the design is
> not clocking (all registers are returning '0' and there is no response
> to inputs). The only differences between the builds are the number of
> times the "channel module" is generated, a modification to a priority
> LUT, and a different adder to sum all the outputs of each "channel
> module". All timing constraints are met.
>
> I have tried a number of things: Different reset logic on the DCMs,
> removing the DCMs altogether and just using the IBUFGs and BUFGs,
> using a non-ES version of the chip, etc. Nothing seems to work. Does
> anyone have any ideas?
>
> Thanks
>
> To send private email:
> [email protected]
> where
> "xy" = "ed.agunos"


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  #3 (permalink)  
Old 12-30-2003, 10:32 PM
Ken Morrow
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Posts: n/a
Default Re: virtex-II problems

Could well be incorrect logic produced by an error in the synthesiser.

I seem to be finding a lot of these recently.

Try running a post place and route simulation. to check for this, if
possible.

Good Luck,

Ken,
Morrow Electronics Limited.

"Mark Schellhorn" <[email protected]> wrote in message
news:[email protected] ..
> Try looking in the Answers Database for ES "anomalies" that might be

biting you.
> I searched on XC2V6000-6 ES and came up with a bunch of potential hits

like this
> one regarding quadrant restrictions for IBUFG routing:
>
>

http://support.xilinx.com/xlnx/xil_a...PagePath=11756
>
> There are other ES errata that apply to DCM usage, but you say that you've
> already tried running without DCMs.
>
> Mark
>
>
> ed wrote:
> > I'm building a multi-channel frequency synthesizer in a Xilinx
> > XC2V6000-6 ES. I have verified a one and two channel build, but when I
> > move to four channels the design stops working (slice usage goes from
> > 12% with one channel to 50% with four). It looks as if the design is
> > not clocking (all registers are returning '0' and there is no response
> > to inputs). The only differences between the builds are the number of
> > times the "channel module" is generated, a modification to a priority
> > LUT, and a different adder to sum all the outputs of each "channel
> > module". All timing constraints are met.
> >
> > I have tried a number of things: Different reset logic on the DCMs,
> > removing the DCMs altogether and just using the IBUFGs and BUFGs,
> > using a non-ES version of the chip, etc. Nothing seems to work. Does
> > anyone have any ideas?
> >
> > Thanks
> >
> > To send private email:
> > [email protected]
> > where
> > "xy" = "ed.agunos"

>



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