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Old 04-01-2005, 11:18 AM
Stephane
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Default Virtex DCM phase alignment and CLK2X registering

When a DCM is locked, can I be sure that CLK0 and CLK2X are perfectly
phase-aligned?
(Virtex-4 DCM_BASE Unisim model seems to show this.)

Actually, I want to register a IOB signal on CLK0 and use it with an
internal CLK2X clock. The problem is: how to know which is the 'good'
rising edge of CLK2X ?

Can I drive the IOB register with CLK2X and enable it with the condition
(CLK0='0') ? I think I don't respect the EN hold time of the register.
And the compiler may shout on me for testing a clock!

Maybe a 1 bit counter that starts on LOCKED='1' has the same waveform as
CLK0 and will not produce a gated clock warning?

Thanks for help,
Stephane
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Old 04-01-2005, 01:40 PM
Marc Randolph
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Default Re: Virtex DCM phase alignment and CLK2X registering

Stephane wrote:
> When a DCM is locked, can I be sure that
> CLK0 and CLK2X are perfectly phase-aligned?


Howdy Stephane,

There is no such thing as "perfectly aligned" in the real world! :-)
The datasheet specs "CLKOUT_PHASE", the phase offset between any DCM
outputs, just for this.

In general though, Xilnx says that you can treat the phase alignment of
the outputs as close enough that you can transfer data between them.
Many people, myself included, have succesfully done just that. There
have been a few reports of problems doing this when there is extra
jitter on the input clock, or even jitter induced from nearby pins.

> Actually, I want to register a IOB signal on CLK0 and use it
> with an internal CLK2X clock. The problem is: how to know which
> is the 'good' rising edge of CLK2X ?


Since CLK0 doesn't change on the falling edge of CLK2X, how about using
that falling edge to sample CLK0 and determine its phase?

> Can I drive the IOB register with CLK2X and enable it with the
> condition (CLK0='0')? I think I don't respect the EN hold time of
> the register. And the compiler may shout on me for testing a clock!


Try it and see what the tools say - that's what timing analyzer is for.
When a clock goes to non-clock destinations, I believe you have the
same guarantees as general logic: no hold time problems. But with the
global clock delay as large as it is on the V4, I'm a little curious if
that's still the case.

> Maybe a 1 bit counter that starts on LOCKED='1' has the same
> waveform as CLK0 and will not produce a gated clock warning?


If it is an option, generating the clock enable with a toggling flop in
the CLK2X domain from the start is the best option. Then there is no
chance of prop delay, setup, or hold time issues.

Have fun,

Marc

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