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Old 10-20-2003, 03:40 AM
Kload
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Default Virtex CLB

Hi all,

I've been going over the structure of the Virtex CLBs and something has
me a little confused. The LUTs/function generators appear to have no
clock, so I assume they act a normal logic gates. That is, inputs F/G
are "processed" immediately and glitches are possible as with any array
of logic gates.

If there is no clock, why are there setup and hold time specifications
(relative to the clk) for the F and G inputs?? If there was to be a
setup time for a slice I would have thought it would be defined with
repsect to the output flip flop - something like

delay through LUT + setup of output FF

however flip flop and LUT setup times are listed seperately.

Any clarification will be much appreciated.

Klod



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  #2 (permalink)  
Old 10-20-2003, 04:23 AM
Kload
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Default Re: Virtex CLB

I forgot to add that calculating

delay through LUT + setup of output FF

does not give the listed setup times for the F and G inputs.

Thanks


Kload wrote:

> Hi all,
>
> I've been going over the structure of the Virtex CLBs and something has
> me a little confused. The LUTs/function generators appear to have no
> clock, so I assume they act a normal logic gates. That is, inputs F/G
> are "processed" immediately and glitches are possible as with any array
> of logic gates.
>
> If there is no clock, why are there setup and hold time specifications
> (relative to the clk) for the F and G inputs?? If there was to be a
> setup time for a slice I would have thought it would be defined with
> repsect to the output flip flop - something like
>
> delay through LUT + setup of output FF
>
> however flip flop and LUT setup times are listed seperately.
>
> Any clarification will be much appreciated.
>
> Klod
>
>
>


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  #3 (permalink)  
Old 10-20-2003, 10:56 AM
Christian Haase
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Default Re: Virtex CLB

Hello Kload,

maybe a look at the SRL16 feature of the LUT helps?

Christian

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