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Old 09-14-2007, 01:26 AM
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Default Virtex-4 PCB design

Xilinx posts gerber file in *.pho format on their website for all of
the evaluation boards. Does anyone no how to import these into
cadence OrCad? or what tool they used to design them in?
Thanks,

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Old 09-17-2007, 04:24 PM
Gabor
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Default Re: Virtex-4 PCB design

On Sep 13, 7:26 pm, [email protected] wrote:
> Xilinx posts gerber file in *.pho format on their website for all of
> the evaluation boards. Does anyone no how to import these into
> cadence OrCad? or what tool they used to design them in?
> Thanks,



Gerber files are like printouts. They were designed to run X/Y photo-
plotters. There are a number of Gerber file viewers available on the
web, some of them are free. It is also possible to generate a
netlist from a set of Gerbers, but you won't have meaningful net
names unless they were embedded in the files. It is unlikely that
you can get back the design database from the Gerber files. This
is a little like trying to get source code from a .bit file in
an FPGA.

The .pho file extension (for photoplot) may indicate that the
design database was PADS. AFAIK there is no common standard for
filename extension of gerber files, although the file format
itself is well defined (usually RS-274X).

I use a viewer from pentalogix called ViewmasterEZ, which is not
free, but it is cheap. It allows editing of Gerber files as well
as some rudimentary design-rule checking. This sort of tool is
extremely useful if you design PCB's, because there is often a
"disconnect" between the design database and the final deliverables
for laminate fabrication. One of the other engineers here uses
a package called Gerbtool (IIRC) and that one has more features
including netlist generation.

HTH,
Gabor

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