FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-28-2005, 10:50 PM
Udo
Guest
 
Posts: n/a
Default Virtex-4 DSP48 - special features (Peter Alfke?)

Hello,

in the "XtremeDSP for Virtex-4 FPGAs User Guide", on
Page 56 are in Table 1-13 some interesting functions
mentioned, like AND and XOR and so on.
Does anyone know how these functions are accomplished?
Is there any documentation available which describes
other more or less hidden (secret?) features of the
DSP48 block?

Many thanks!
Udo

Reply With Quote
  #2 (permalink)  
Old 10-29-2005, 11:38 PM
comcast
Guest
 
Posts: n/a
Default Re: Virtex-4 DSP48 - special features (Peter Alfke?)

> in the "XtremeDSP for Virtex-4 FPGAs User Guide", on
> Page 56 are in Table 1-13 some interesting functions
> mentioned, like AND and XOR and so on.
> Does anyone know how these functions are accomplished?


AND function: result is 1 when all the input bits are 1, otherwise the
result is 0. So if you add 1 to the input, what will you get (hint: carry
out)?

XOR:
a = 0, b = 0, result = 0
a = 0, b = 1, result = 1
a = 1, b = 0, result = 1
a = 1, b = 1, result = 0

if you add a and b, you get

a = 0, b = 0, result = 00
a = 0, b = 1, result = 01
a = 1, b = 0, result = 01
a = 1, b = 1, result = 10

result(0) is what you need.

HTH,
Jim


Reply With Quote
  #3 (permalink)  
Old 10-31-2005, 06:29 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Virtex-4 DSP48 - special features (Peter Alfke?)

These functions are accomplished by a "trick".
The hardware can only perform mathematical operation, with carry.
But by grounding every odd input, and ignoring every odd output, the
carry does not propagate. Essentially, this divides the
adder/subtractor into "watertight one-bit compartments".
Peter Alfke, Xilinx Applications

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Peter Alfke's SPDT Switch Debouncer [email protected] FPGA 18 08-22-2005 08:13 PM
Virtex-4: DSP48 Fmax missing? William FPGA 3 10-22-2004 01:54 PM
Paging Peter Alfke (3S1000 pricing) Pete Fraser FPGA 4 09-15-2003 11:34 PM


All times are GMT +1. The time now is 03:50 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved