FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-18-2004, 05:26 AM
William
Guest
 
Posts: n/a
Default Virtex-4: DSP48 Fmax missing?

There is no Fmax reported when I instantiated a DSP48 with internal
input and output registers turned on. Anyone have any ideas, why this
happened?

Thanks.
Reply With Quote
  #2 (permalink)  
Old 10-20-2004, 10:19 PM
Vic Vadi
Guest
 
Posts: n/a
Default Re: Virtex-4: DSP48 Fmax missing?

Hi William,

Did you include a timing constraint of some ns on
your clock in the ucf file?

- Vic

William wrote:

> There is no Fmax reported when I instantiated a DSP48 with internal
> input and output registers turned on. Anyone have any ideas, why this
> happened?
>
> Thanks.


Reply With Quote
  #3 (permalink)  
Old 10-22-2004, 01:44 PM
William
Guest
 
Posts: n/a
Default Re: Virtex-4: DSP48 Fmax missing?

Hi Vic,

Yes, I constrained my clock in the UCF. Alternatively, I also tried
the -a option for the TRCE. Both methods give me no Fmax.

Thanks,
Kia Leong

Vic Vadi <[email protected]> wrote in message news:<4176C8[email protected]>...
> Hi William,
>
> Did you include a timing constraint of some ns on
> your clock in the ucf file?
>
> - Vic
>
> William wrote:
>
> > There is no Fmax reported when I instantiated a DSP48 with internal
> > input and output registers turned on. Anyone have any ideas, why this
> > happened?
> >
> > Thanks.

>
> --

Reply With Quote
  #4 (permalink)  
Old 10-22-2004, 01:54 PM
William
Guest
 
Posts: n/a
Default Re: Virtex-4: DSP48 Fmax missing?

Hi Vic,

Yes, I constrained the clock in the UCF. Alternatively, I also tried
the -a option for the TRCE. Both methods give me no Fmax.

Thanks


Vic Vadi <[email protected]> wrote in message news:<[email protected]>...
> Hi William,
>
> Did you include a timing constraint of some ns on
> your clock in the ucf file?
>
> - Vic
>
> William wrote:
>
> > There is no Fmax reported when I instantiated a DSP48 with internal
> > input and output registers turned on. Anyone have any ideas, why this
> > happened?
> >
> > Thanks.

>
> --

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
SystemC Missing Libraries ac Verilog 1 12-21-2004 08:19 AM
If you need higher fmax for your FPGA design Maximum Frequency FPGA 0 06-17-2004 08:03 AM
okay what am I missing??? Please juice28 FPGA 0 07-04-2003 03:56 AM


All times are GMT +1. The time now is 09:23 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved