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Old 01-15-2004, 08:16 PM
Adarsh Kumar Jain
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Posts: n/a
Default Virtex 2 Pro : Rocket IO Simulation Problem

Hi,
I am using a Virtex 2 Pro (V2P7) device to perform some deserialization and
8b/10b decoding.
I use ISE 6.1SP3 and Active HDL 6.1 SP2.
Its a very simple design and right now all I am trying to do is to get
something out of the tranceiver.
The code is given below :

The DCM parts simulate ok but I am not sure about how to drive the RXP and
RXN inputs to the Transceiver.
I try to feed opposite polarity clocks into them in the hope that at least
Recoverd Clock i should get to see.
But i see nothing...
Any help will be apprecaiated,
Thanks in advance

//Top Level
module GT_TOP
(DinP,DinN,ClkP,ClkN,Dout,DCMLocked,RefClk80,UsrCl k,RXRECCLK,RXRESET);

input DinP;
input DinN;
input ClkP,ClkN;
input RXRESET;
output [15:0] Dout;
output DCMLocked;
output RefClk80;
output UsrClk;
output RXRECCLK;


// ************************************************** ******************
// ******************** CLOCK SECTION *****************
// *********************************************

// XST is stupid at handling clocks and clock buffer, so we instantiate
// all the buffers and inihbit XST from changing them with the attribute.

wire RefClk80;
wire DCMLocked;
wire UsrClk,DCMClkFBOut,DCMUsrClk,DCMClkFBIn;

// Instantiate the Differential Global Input Buffer
IBUFGDS DIFCLKBUF (.I(ClkP), .IB(ClkN), .O(RefClk80) );
//synthesis attribute clock_buffer of ClkP is "none"
//synthesis attribute clock_buffer of ClkN is "none"

BUFG USRCLKBUF (.I(DCMUsrClk), .O(UsrClk)); // Use this output as
User clock to GTs
//synthesis attribute clock_buffer of DCMUsrClk is "none"
BUFG FBCLKBUF (.I(DCMClkFBOut), .O(DCMClkFBIn)); // clock for feedback
//synthesis attribute clock_buffer of DCMClkFBOut is "none"

// synthesis translate_off
defparam DCMGT.DUTY_CYCLE_CORRECTION = "TRUE";
defparam DCMGT.FACTORY_JF = 16'hC080;
defparam DCMGT.CLKDV_DIVIDE = 2.0;
defparam DCMGT.CLKFX_DIVIDE = 1;
defparam DCMGT.CLKFX_MULTIPLY = 4;
defparam DCMGT.CLKOUT_PHASE_SHIFT = "NONE";
defparam DCMGT.CLK_FEEDBACK = "1X";
defparam DCMGT.DLL_FREQUENCY_MODE = "LOW";
defparam DCMGT.PHASE_SHIFT = 0;
defparam DCMGT.SIM_CLKIN_CYCLE_JITTER = 300;
defparam DCMGT.SIM_CLKIN_PERIOD_JITTER = 1000;
defparam DCMGT.MAXPERCLKIN = 41668;
defparam DCMGT.MAXPERPSCLK = 1264998735;
//synthesis translate_on

//synthesis attribute CLKDV_DIVIDE of DCMGT is "2.0"
//synthesis attribute DUTY_CYCLE_CORRECTION of DCMGT is "TRUE"
DCM DCMGT
(
.CLK0 (DCMClkFBOut),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (),
.CLKDV (DCMUsrClk),
.CLKFX (),
.CLKFX180 (),
.LOCKED (DCMLocked),
.PSDONE (),
.STATUS (),
.CLKFB (DCMClkFBIn),
.CLKIN (RefClk80),
.DSSEN (1'b0),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (1'b0)
);

wire RXRESET;

wire [1:0] RXBUFSTATUS;
wire [1:0] RXCHARISCOMMA;
wire [1:0] RXCHARISK;
wire RXCOMMADET;
wire [1:0] RXDISPERR;
wire [1:0] RXLOSSOFSYNC;
wire [1:0] RXNOTINTABLE;
wire RXREALIGN;
wire RXRECCLK;
wire [1:0] RXRUNDISP;


gtmacro1 GT1 (
.CONFIGENABLE(1'b0),
.CONFIGIN(1'b0),
.ENMCOMMAALIGN(1'b0),
.ENPCOMMAALIGN(1'b0),
.POWERDOWN(1'b0),
.REFCLK(RefClk80),
.REFCLK2(RefClk80),
.REFCLKSEL(1'b0),
.RXN(DinN),
.RXP(DinP),
.RXPOLARITY(1'b0),
.RXRESET(RXRESET),
.RXUSRCLK(UsrClk),
.RXUSRCLK2(UsrClk),
.TXUSRCLK(UsrClk),
.TXUSRCLK2(UsrClk),
.CONFIGOUT(),
.RXBUFSTATUS(RXBUFSTATUS),
.RXCHARISCOMMA(RXCHARISCOMMA),
.RXCHARISK(RXCHARISK),
.RXCLKCORCNT(),
.RXCOMMADET(RXCOMMADET),
.RXDATA(Dout),
.RXDISPERR(RXDISPERR),
.RXLOSSOFSYNC(RXLOSSOFSYNC),
.RXNOTINTABLE(RXNOTINTABLE),
.RXREALIGN(RXREALIGN),
.RXRECCLK(RXRECCLK),
.RXRUNDISP(RXRUNDISP)
);


endmodule

// instantiation of the macro
module gtmacro1(
CONFIGENABLE,
CONFIGIN,
ENMCOMMAALIGN,
ENPCOMMAALIGN,
POWERDOWN,
REFCLK,
REFCLK2,
REFCLKSEL,
RXN,
RXP,
RXPOLARITY,
RXRESET,
RXUSRCLK,
RXUSRCLK2,
TXUSRCLK,
TXUSRCLK2,
CONFIGOUT,
RXBUFSTATUS,
RXCHARISCOMMA,
RXCHARISK,
RXCLKCORCNT,
RXCOMMADET,
RXDATA,
RXDISPERR,
RXLOSSOFSYNC,
RXNOTINTABLE,
RXREALIGN,
RXRECCLK,
RXRUNDISP);

input CONFIGENABLE;
input CONFIGIN;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input POWERDOWN;
input REFCLK;
input REFCLK2;
input REFCLKSEL;
input RXN;
input RXP;
input RXPOLARITY;
input RXRESET;
input RXUSRCLK;
input RXUSRCLK2;
input TXUSRCLK;
input TXUSRCLK2;

output CONFIGOUT;
output [1:0] RXBUFSTATUS;
output [1:0] RXCHARISCOMMA;
output [1:0] RXCHARISK;
output [2:0] RXCLKCORCNT;
output RXCOMMADET;
output [15:0] RXDATA;
output [1:0] RXDISPERR;
output [1:0] RXLOSSOFSYNC;
output [1:0] RXNOTINTABLE;
output RXREALIGN;
output RXRECCLK;
output [1:0] RXRUNDISP;


GT_ETHERNET_2 GT_ETHERNET_INST(
.CONFIGENABLE (CONFIGENABLE),
.CONFIGIN (CONFIGIN),
.ENMCOMMAALIGN (ENMCOMMAALIGN),
.ENPCOMMAALIGN (ENPCOMMAALIGN),
.LOOPBACK (2'b00),
.POWERDOWN (POWERDOWN),
.REFCLK (REFCLK),
.REFCLK2 (REFCLK2),
.REFCLKSEL (REFCLKSEL),
.BREFCLK (1'b0),
.BREFCLK2 (1'b0),
.RXN (RXN),
.RXP (RXP),
.RXPOLARITY (RXPOLARITY),
.RXRESET (RXRESET),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.TXBYPASS8B10B (2'b00),
.TXCHARDISPMODE (2'b00),
.TXCHARDISPVAL (2'b00),
.TXCHARISK (2'b00),
.TXDATA (16'b0000000000000000),
.TXFORCECRCERR (1'b0),
.TXINHIBIT (1'b0),
.TXPOLARITY (1'b0),
.TXRESET (1'b0),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2),
.CONFIGOUT (CONFIGOUT),
.RXBUFSTATUS (RXBUFSTATUS[1:0]),
.RXCHARISCOMMA (RXCHARISCOMMA[1:0]),
.RXCHARISK (RXCHARISK[1:0]),
.RXCHECKINGCRC (),
.RXCLKCORCNT (RXCLKCORCNT[2:0]),
.RXCOMMADET (RXCOMMADET),
.RXCRCERR (),
.RXDATA (RXDATA[15:0]),
.RXDISPERR (RXDISPERR[1:0]),
.RXLOSSOFSYNC (RXLOSSOFSYNC[1:0]),
.RXNOTINTABLE (RXNOTINTABLE[1:0]),
.RXREALIGN (RXREALIGN),
.RXRECCLK (RXRECCLK),
.RXRUNDISP (RXRUNDISP[1:0]),
.TXBUFERR (),
.TXKERR (),
.TXN (),
.TXP (),
.TXRUNDISP ());
// synthesis attribute ALIGN_COMMA_MSB of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CHAN_BOND_LIMIT of GT_ETHERNET_INST is 1
// synthesis attribute CHAN_BOND_MODE of GT_ETHERNET_INST is "OFF"
// synthesis attribute CHAN_BOND_OFFSET of GT_ETHERNET_INST is 0
// synthesis attribute CHAN_BOND_ONE_SHOT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute CHAN_BOND_SEQ_2_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CHAN_BOND_SEQ_LEN of GT_ETHERNET_INST is 1
// synthesis attribute CHAN_BOND_WAIT of GT_ETHERNET_INST is 7
// synthesis attribute CLK_CORRECT_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute CLK_COR_INSERT_IDLE_FLAG of GT_ETHERNET_INST is
"FALSE"
// synthesis attribute CLK_COR_KEEP_IDLE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CLK_COR_REPEAT_WAIT of GT_ETHERNET_INST is 1
// synthesis attribute CLK_COR_SEQ_1_1 of GT_ETHERNET_INST is 00110111100
// synthesis attribute CLK_COR_SEQ_1_2 of GT_ETHERNET_INST is 00001010000
// synthesis attribute CLK_COR_SEQ_1_3 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_1_4 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_1 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_2 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_3 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_4 of GT_ETHERNET_INST is 00000000000
// synthesis attribute CLK_COR_SEQ_2_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute CLK_COR_SEQ_LEN of GT_ETHERNET_INST is 2
// synthesis attribute COMMA_10B_MASK of GT_ETHERNET_INST is 1111111000
// synthesis attribute CRC_END_OF_PKT of GT_ETHERNET_INST is "K29_7"
// synthesis attribute CRC_FORMAT of GT_ETHERNET_INST is "ETHERNET"
// synthesis attribute CRC_START_OF_PKT of GT_ETHERNET_INST is "K27_7"
// synthesis attribute DEC_MCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute DEC_PCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute DEC_VALID_COMMA_ONLY of GT_ETHERNET_INST is "TRUE"
// synthesis attribute MCOMMA_10B_VALUE of GT_ETHERNET_INST is 1100000000
// synthesis attribute MCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute PCOMMA_10B_VALUE of GT_ETHERNET_INST is 0011111000
// synthesis attribute PCOMMA_DETECT of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_BUFFER_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_CRC_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute RX_DATA_WIDTH of GT_ETHERNET_INST is 2
// synthesis attribute RX_DECODE_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute RX_LOSS_OF_SYNC_FSM of GT_ETHERNET_INST is "FALSE"
// synthesis attribute RX_LOS_INVALID_INCR of GT_ETHERNET_INST is 1
// synthesis attribute RX_LOS_THRESHOLD of GT_ETHERNET_INST is 4
// synthesis attribute TERMINATION_IMP of GT_ETHERNET_INST is 50
// synthesis attribute SERDES_10B of GT_ETHERNET_INST is "TRUE"
// synthesis attribute TX_BUFFER_USE of GT_ETHERNET_INST is "TRUE"
// synthesis attribute TX_CRC_FORCE_VALUE of GT_ETHERNET_INST is 11010110
// synthesis attribute TX_CRC_USE of GT_ETHERNET_INST is "FALSE"
// synthesis attribute TX_DATA_WIDTH of GT_ETHERNET_INST is 2
// synthesis attribute TX_DIFF_CTRL of GT_ETHERNET_INST is 500
// synthesis attribute TX_PREEMPHASIS of GT_ETHERNET_INST is 0
// synthesis attribute REF_CLK_V_SEL of GT_ETHERNET_INST is 0
// synthesis translate_off
defparam GT_ETHERNET_INST.CLK_COR_INSERT_IDLE_FLAG="FALSE";
defparam GT_ETHERNET_INST.CLK_COR_KEEP_IDLE="FALSE";
defparam GT_ETHERNET_INST.CLK_COR_REPEAT_WAIT=1;
defparam GT_ETHERNET_INST.RX_CRC_USE="FALSE";
defparam GT_ETHERNET_INST.RX_LOSS_OF_SYNC_FSM="FALSE";
defparam GT_ETHERNET_INST.RX_LOS_INVALID_INCR=1;
defparam GT_ETHERNET_INST.RX_LOS_THRESHOLD=4;
defparam GT_ETHERNET_INST.TERMINATION_IMP=50;
defparam GT_ETHERNET_INST.SERDES_10B="TRUE";
defparam GT_ETHERNET_INST.TX_CRC_FORCE_VALUE=8'b11010110;
defparam GT_ETHERNET_INST.TX_CRC_USE="FALSE";
defparam GT_ETHERNET_INST.TX_DIFF_CTRL=500;
defparam GT_ETHERNET_INST.TX_PREEMPHASIS=0;
defparam GT_ETHERNET_INST.REF_CLK_V_SEL=0;
// synthesis translate_on

endmodule


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