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Old 12-24-2003, 08:45 AM
Jarek
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Default VHDL-Xilinx-Simulation (signal not connected to port) ?

Hi.

How to simulate (observe) signals not connected to port (Xiilinx ISE
WebPack-ModelSim XE).
For example signal counter in project test.vhd.

Best regards
Jarek

-----test.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Test is
Port ( clock: in std_logic; -- system clock (25 MHz)
resetn: in std_logic; -- active low reset
c_out: out std_logic);
end Test;

architecture Behavioral of Test is

signal counter: std_logic_vector(3 downto 0);
begin

COUNT: process (clock, resetn)
begin
if (resetn = '0') then
counter <= (others => '0');
elsif (clock'event and clock = '1') then
counter <= counter + 1;
end if;
end process;

c_out <= counter(3);

end Behavioral;

--------------VHDL Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
constant Period : time := 40 ns; -- 25 MHz System Clock
END testbench;

ARCHITECTURE behavior OF testbench IS

COMPONENT test
PORT(
clock : IN std_logic;
resetn : IN std_logic;
c_out : OUT std_logic
);
END COMPONENT;

SIGNAL clock : std_logic := '0';
SIGNAL resetn : std_logic;
SIGNAL c_out : std_logic;

BEGIN

uut: test PORT MAP(
clock => clock,
resetn => resetn,
c_out => c_out
);

clock <= not clock after (Period / 2);
resetn <= '0', '1' after Period;

tb : PROCESS
BEGIN
wait; -- will wait forever
END PROCESS;

END;


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  #2 (permalink)  
Old 12-28-2003, 06:37 PM
Mike Treseler
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Default Re: VHDL-Xilinx-Simulation (signal not connected to port) ?

Jarek wrote:

> How to simulate (observe) signals not connected to port (Xiilinx ISE
> WebPack-ModelSim XE).
> For example signal counter in project test.vhd.


To see the waveform "counter", try this:

vsim testbench -do "add wave sim:/testbench/uut/*; run 4 uS;"

To use "counter" in a testbench, you can package it,
or bring it out to a port,
or use modelsim signal spy.


-- Mike Treseler

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