FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 02-20-2005, 05:46 AM
fpgawizz
Guest
 
Posts: n/a
Default VHDL State Machine - Literature

Where is a good place to find info on building VHDL moore FSMs? I am trying
to design a vending machine with the following features on a spartan 3
kit.
It has the following features:
1) 5 products price - 55/60/65/70/75c
2) 3 different coin inputs -25 c/10c/5c
3) Need to display the product price and price entered via the 3 coin
inputs.(first 2 digits display coin input values, last 2 digits display
product price, use any digits to display change out)
4) When the value of product selected is reached, it should be dispensed
and any change displayed.
5) System should reset after this and also reset if done asynchronously.

The books I have talk about FSMs for 4-5 pages. Not good enough for me to
start thinking about this the right way.
thanks



Reply With Quote
  #2 (permalink)  
Old 02-20-2005, 08:03 PM
Eric Crabill
Guest
 
Posts: n/a
Default Re: VHDL State Machine - Literature


Hi,

There is a short presentation on modeling
synchronous edge triggered FSMs in Verilog, at:
http://www.engr.sjsu.edu/crabill

The VHDL syntax will be different, but the
modeling techniques are the same.

Hope that helps,
Eric

fpgawizz wrote:
>
> Where is a good place to find info on building VHDL moore FSMs? I am trying
> to design a vending machine with the following features on a spartan 3
> kit.
> It has the following features:
> 1) 5 products price - 55/60/65/70/75c
> 2) 3 different coin inputs -25 c/10c/5c
> 3) Need to display the product price and price entered via the 3 coin
> inputs.(first 2 digits display coin input values, last 2 digits display
> product price, use any digits to display change out)
> 4) When the value of product selected is reached, it should be dispensed
> and any change displayed.
> 5) System should reset after this and also reset if done asynchronously.
>
> The books I have talk about FSMs for 4-5 pages. Not good enough for me to
> start thinking about this the right way.
> thanks

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
About finite state machine Chih-Hsu Yen Verilog 1 03-14-2006 10:50 AM
Monolithic state machine or structured state machine? vax,3900 FPGA 6 05-12-2004 03:06 AM
please help! state machine Simone Winkler FPGA 4 01-05-2004 11:33 AM


All times are GMT +1. The time now is 06:15 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved