FPGA Central

Help!

I have a state machine on my top level for an SRAM controller. The states
are sram_state_read, sram_state_write, sram_state_idle, and
sram_state_reset. Presently the design is flat with no components. I want to
put the SRAM paths in a component by itself. Since the SRAM state machine
may influence other parts of the design, I want to have a separate component
for it, or leave it in the top level. Now it seems to me that one should be
able to pass these states down to to the SRAM paths' component using the
type that I decleare on the top level. However I have been unable to find
the syntax for doing this. I suppose I could "hard code" the states into
known patterns of 1s and 0s and pass the the info into the component using
std_logic_vector but this seems counter to high level language philosophy.
Can anybody help?

Thanks,
Brad Smallridge
b r a d @ a i v i s i o n. c o m

Brad,

This will work if you declare the state types in a separate package file.

Joe

Brad,
I tend not to pass the state of a statemachine
to other blocks. I tend to do the following
steps:
1) Draw block diagram for statemachine and
datapath/resource blocks the statemachine
controls.
2) Draw bubble diagram (on paper) for statemachine.
3) Factor out any additional resources out of the
statemachine (such as incrementers) and put
them in separate processes or separate components.
4) Code all datapath and resource blocks
5) Fix bubble diagram as when you code the datapath
it is typical that you need something different than
in your original plan.
6) Code statemachine from bubble diagram.

Keep in mind that every designer probably has their
own method, but this ought to get you started.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~




> Help!
>
> I have a state machine on my top level for an SRAM controller. The states
> are sram_state_read, sram_state_write, sram_state_idle, and
> sram_state_reset. Presently the design is flat with no components. I want to
> put the SRAM paths in a component by itself. Since the SRAM state machine
> may influence other parts of the design, I want to have a separate component
> for it, or leave it in the top level. Now it seems to me that one should be
> able to pass these states down to to the SRAM paths' component using the
> type that I decleare on the top level. However I have been unable to find
> the syntax for doing this. I suppose I could "hard code" the states into
> known patterns of 1s and 0s and pass the the info into the component using
> std_logic_vector but this seems counter to high level language philosophy.
> Can anybody help?
>
> Thanks,
> Brad Smallridge
> b r a d @ a i v i s i o n. c o m
>
>
>