FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-07-2005, 04:09 PM
Tony Acquah
Guest
 
Posts: n/a
Default VHDL algorithm/code for implementing QAM on FPGA

Hello Everyone,
I am working on designing a digital modulator that will implement QAM
on FPGA.

The FPGA will be programmed in VHDL to modulate an input
signal(maybefrom a function generator)

A D/A converter will convert the digital signal to an analog one that
canbe transmitted.

Anyway, what I need now is algorithm and/or VHDL code that will carry
out the QAM on FPGA.

Any help is greatly appreciated

Anthony

Reply With Quote
  #2 (permalink)  
Old 11-07-2005, 10:58 PM
Bevan Weiss
Guest
 
Posts: n/a
Default Re: VHDL algorithm/code for implementing QAM on FPGA

Tony Acquah wrote:
> Hello Everyone,
> I am working on designing a digital modulator that will implement QAM
> on FPGA.
>
> The FPGA will be programmed in VHDL to modulate an input
> signal(maybefrom a function generator)
>
> A D/A converter will convert the digital signal to an analog one that
> canbe transmitted.
>
> Anyway, what I need now is algorithm and/or VHDL code that will carry
> out the QAM on FPGA.
>
> Any help is greatly appreciated
>
> Anthony


Which form of QAM do you want to use?
This could be as simple as a look up table for most small inputs, I'd
probably use it for 16-QAM and up to 256-QAM. Which is probably all
you're going to target anyways.

If this is the only thing that you'll have in the chip it's probably
worth adding in some FEC coding as well. This would allow you to use
TCM, and hence provide slightly better performance under noisy conditions.

I note that you want to use a function generator to create the input
waveforms. This would generally be a serial train of digital pulses,
and perhaps a clock signal (or the clocking may be intrinsic to the
digital pulses ala Manchester encoding). The serial to parallel
converter is simply a shift register, which is clocked in x number of
times, then read out in parallel, then clocked in an additional x times
etc. There is probably a standard block for this that would be faster
in most cases than a manual implementation.
There is likely a standard block for the ROM to use as the QAM lookup
table. And if you wanted to implement TCM then I'm sure there's some
code around for a viterbi algorithm, and the convolutional generator.
Reply With Quote
  #3 (permalink)  
Old 11-08-2005, 12:06 AM
Ray Andraka
Guest
 
Posts: n/a
Default Re: VHDL algorithm/code for implementing QAM on FPGA



The coder is just a remapping of the input I and Q bits to the IQ
plane. It is a straight-forward mapping whch usually does not need a
table. For example, QAM64 uses 6 bit symbols. 3 bits each specify I
and Q independently. Those 3 bits take on values +/-1, +/-3, +/-5 and
+/-7. There will also need to be a nyquist filter to limit the spectral
footprint and a modulator. If desired, there may also be a
convolutional encoder preceding the symbol conversion to I and Q.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email [email protected]
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
verilog code for the "international data encryption algorithm(IDEA)" neelima Verilog 0 01-23-2007 11:09 AM
How to convert a algorithm to verilog code. naran Verilog 3 01-19-2007 12:57 PM
Implementing control registers (VHDL) Sylvain Munaut FPGA 5 07-29-2004 06:27 PM
Implementing multiple registers with one single input output bus and address select in VHDL. James Williams FPGA 1 10-06-2003 10:45 PM


All times are GMT +1. The time now is 12:25 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved