FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 04-11-2006, 04:19 AM
Guest
 
Posts: n/a
Default very slow pull-up with CPLD design

We are using a Lattice LC4256V CPLD for a new design and we're having
some problems with open drain outputs + 5V pullups. We've debuged and
removed items from the system to the point where we have the single
CPLD (pins configured 3.3v CMOS open drain) connected to a 4.7K
resistor to +5V.

We configured the pins to output a 4MHz square wave for testing. When
we hook a scope up to the pins, we see that the voltage rises at a very
slow rate at the high edge of the clock pulse and only makes it to
about 2V before the falling edge takes the output low. When we remove
the pullups and set the pins to normal 3.3V mode we get a clean square
wave, it is only when using pullups that problems are created.

Any ideas on why the pullup is taking so long to bring the pin voltage
to 5V? We have used 4.7K pullups with other FPGA / CPLD designs before
in designs faster than 4 MHz without any problems. Doing the math, it
seems the acting capacitence from the CPLD is something like 15uF to
have the pullup rise so slowly. Am I doing something wrong here?

Reply With Quote
  #2 (permalink)  
Old 04-11-2006, 04:56 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: very slow pull-up with CPLD design

[email protected] wrote:
> We are using a Lattice LC4256V CPLD for a new design and we're having
> some problems with open drain outputs + 5V pullups. We've debuged and
> removed items from the system to the point where we have the single
> CPLD (pins configured 3.3v CMOS open drain) connected to a 4.7K
> resistor to +5V.
>
> We configured the pins to output a 4MHz square wave for testing. When
> we hook a scope up to the pins, we see that the voltage rises at a very
> slow rate at the high edge of the clock pulse and only makes it to
> about 2V before the falling edge takes the output low. When we remove
> the pullups and set the pins to normal 3.3V mode we get a clean square
> wave, it is only when using pullups that problems are created.
>
> Any ideas on why the pullup is taking so long to bring the pin voltage
> to 5V? We have used 4.7K pullups with other FPGA / CPLD designs before
> in designs faster than 4 MHz without any problems. Doing the math, it
> seems the acting capacitence from the CPLD is something like 15uF to
> have the pullup rise so slowly. Am I doing something wrong here?


The maths is suspect if you get 15uF.

4MHz is 125ns H/L, and a 125 ns Tau, is 26pF/4K7

So, your symptoms indicate ~26pf system c : That is highish,
but not outlandish. What else is this connected to :
Loads, track etc ?

Simple solution is to lower the pullup...

-jg



Reply With Quote
  #3 (permalink)  
Old 04-12-2006, 05:05 AM
Daniel Lang
Guest
 
Posts: n/a
Default Re: very slow pull-up with CPLD design

"Jim Granville" <[email protected]> wrote in message
news:[email protected]
> [email protected] wrote:
>> We are using a Lattice LC4256V CPLD for a new design and we're having
>> some problems with open drain outputs + 5V pullups. We've debuged and
>> removed items from the system to the point where we have the single
>> CPLD (pins configured 3.3v CMOS open drain) connected to a 4.7K
>> resistor to +5V.
>>
>> We configured the pins to output a 4MHz square wave for testing. When
>> we hook a scope up to the pins, we see that the voltage rises at a very
>> slow rate at the high edge of the clock pulse and only makes it to
>> about 2V before the falling edge takes the output low. When we remove
>> the pullups and set the pins to normal 3.3V mode we get a clean square
>> wave, it is only when using pullups that problems are created.
>>
>> Any ideas on why the pullup is taking so long to bring the pin voltage
>> to 5V? We have used 4.7K pullups with other FPGA / CPLD designs before
>> in designs faster than 4 MHz without any problems. Doing the math, it
>> seems the acting capacitence from the CPLD is something like 15uF to
>> have the pullup rise so slowly. Am I doing something wrong here?

>
> The maths is suspect if you get 15uF.
>
> 4MHz is 125ns H/L, and a 125 ns Tau, is 26pF/4K7
>
> So, your symptoms indicate ~26pf system c : That is highish,
> but not outlandish. What else is this connected to :
> Loads, track etc ?
>
> Simple solution is to lower the pullup...


I would suggest a 1K pullup.

Also, a conventional 10x passive scope probe can add 10 to 12pF of
capacitance to the circuit. You should use a 10x active probe with
less than 1pF of input capacitance to see what is going on.

Daniel Lang


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
CPLD design software under WINE? Mika Leinonen FPGA 4 10-18-2005 07:45 PM
Motion controller design with CPLD Leeinhyuk FPGA 1 06-09-2005 06:22 PM
Motion controller design with CPLD Leeinhyuk FPGA 1 06-09-2005 09:06 AM
Hve to know the pin connection between cpld and fpga in my design senthil FPGA 0 10-12-2004 02:48 PM
Xilinx XC9500 CPLD internal pull-up?? Bruno Cardeira FPGA 3 07-22-2004 09:12 PM


All times are GMT +1. The time now is 04:29 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved