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Old 04-10-2006, 06:40 PM
Fizzy
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Default Very basic question

Hi,

If i have a design based on system generator and i do not have any
clock input to that do i still need clock input when i would be putting
that logic on FPGA. I know its very very nive and basic question but
need to remove some questions about clocking in FPGA. Why do we need
clock on FPGA when our design does not have any clock input.

Thanks

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Old 04-10-2006, 07:04 PM
John_H
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Default Re: Very basic question

"Fizzy" <[email protected]> wrote in message
news:[email protected] oups.com...
....
> Why do we need
> clock on FPGA when our design does not have any clock input[?]


Most FPGAs step through several processes in sequence rather than being a
simple multiple-input multiple-output combinatorial circuit.

When registers are used, they are often coordinated to be "in step" with
each other so if two values change at roughly the same time, they are made
to absolutely change at the same time or absolutely not change at the same
time.

Another problem with some combinatorial logic is the glitch. If you change
one and only one input, you may get a glitch on a signal that ordinarily
wouldn't change. A change on one input can often have several paths that it
takes to affect one output; if these paths have different delays, one path
can invert the output before the other path "corrects" the output back to
the original logic level.

It's rare that an FPGA design implements logic that doesn't need a sequence
of steps - sequential logic - to produce a result. If your design only
needs results at 1 MHz update rates, you can accomplish much in that 1000 ns
time period. Most designs want to work on a higher data throughput which
requires "pipelining" through many steps to divide the processing into many
stages of several nanoseconds each rather than 100s of nanosecods for a full
operation.


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Old 04-11-2006, 05:10 AM
Tommy Thorn
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Default Re: Very basic question

John_H wrote:
> "Fizzy" <[email protected]> wrote in message
> news:[email protected] oups.com...
> ...
>> Why do we need
>> clock on FPGA when our design does not have any clock input[?]


John is right of course, but to make it perfectly clear: if you have no
clocked logic, that is, all your output are combinatorial functions of
the input, then you don't need to provide a clock to your FPGA at all
and the design will still work as expected.

However, using an FPGA in such a situation would be wasting most of the
expensive machinery that is an FPGA. Maybe you only really need a CPLD.

Tommy
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Old 04-12-2006, 07:41 AM
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Default Re: Very basic question

Hi,
FPGA are already provided on-chip oscillator.
If user don't want to use ext oscillator as a clock source;he can use
internal,but the limitation is of the frequency of onchip oscillator.
Is ur question get answer?
if not then pls elaboarate more.

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