Al Clark wrote:
>
> Jim Lewis <[email protected]> wrote in
> news:[email protected]:
>
> > Al,
> > Also note that Verilog /= VHDL
> >
> > If you are interested in VHDL, I like:
> > A VHDL Primer by J Bhasker.
> >
> > Cheers,
> > Jim
>
> Thanks Jim,
>
> I know that Verilog is not VHDL. I was just trying to point out that I
> don't have that background either.
>
> I am using Verilog because a portion of my project was already written in
> Verilog by someone else.
One suggestion, always write your synthesizable code from the examples
given by the tool vendors. Both VHDL and Verilog will compile and
simulate code that can no be synthesized. So design your hardware
first, as a block diagram or in any other form that lets you see the
registers and blocks of logic. Then write your code using the examples
the vendors provide for the various blocks in your diagram.
When used to build hardware, HDLs are not programming languages. They
are hardware description languages, hence HDL, not HPL.
--
Rick "rickman" Collins
[email protected]
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and
FPGA design URL
http://www.arius.com
4 King Ave 301-682-7772 Voice
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