FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 07-27-2007, 03:09 PM
Aaron Chen
Guest
 
Posts: n/a
Default V5 Differential Select I/O

Xilinx V5 supports Differential select I/O data rate upto 1250 Mbps. It supports HT_25, LVDS_25 and may other electrical standards. What electrical standard should be used to support the maximum specified data rate of 1250 Mbps? My preference will be HT_25 as it is easy to meet the common mode voltage specification but I am not sure if I can achieve the highest supported data rate with the HT_25 electrical standard.

The LVDS_25 has typical input common mode voltage of 1.2V while the HT_25 has typical input common mode voltage of 600mV. I understand that LVDS_25 has very wide common mode voltage range. But do I get the highest specified data rate if I do not follow they typical voltage specification?

LVDS_25 I think is the most popular standard. Do I have to use 1.2V input common mode voltage for 1.25 Gbps operation? or Can I still get 1.25 Gbps with HT_25 at 600mV input common mode voltage?

Thanks

Aaron
Reply With Quote
  #2 (permalink)  
Old 07-27-2007, 03:42 PM
austin
Guest
 
Posts: n/a
Default Re: V5 Differential Select I/O

Aaron,

That is why people use signal integrity simulation tools: without
running a simulation for your pcb traces, and your driving/driven
device(s), your question can not be answered.

The 1.25 Gbs also presumes double data rate (DDR).

A quick "what if" using Hyperlynx SI tool, shows both standards are
capable of the speed (ie they switch fast enough, 'eye' is open), but a
full simulation for your situation would be required to have confidence
that it would work at this speed.

Austin
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
differential I/O with ISE 8.2 / spartan3E [email protected] FPGA 2 12-07-2006 09:56 PM
32 bit select map [email protected] FPGA 0 02-28-2006 02:28 PM
spartan3 differential I/O Marco FPGA 3 01-10-2006 03:38 AM
differential clock in EDK Johan Bernspång FPGA 6 11-02-2005 03:47 PM
How to select a FPGA FPGA 5 10-17-2003 10:10 PM


All times are GMT +1. The time now is 11:38 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2024, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved