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Old 11-14-2007, 05:34 PM
Jan Pech
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Default USR_ACCESS_VIRTEX4 usage

Hello all,

I would like to use the USR_ACCESS_VIRTEX4 primitive to access an
additional bitstream stored in a config flash. The situation is
following:
* I have a master FPGA (Virtex-4FX) and a slave FPGA (Spartan-3A). The
slave FPGA is located on an additional board and it is NOT daisy-chained
with the master one.
* Master FPGA gets configured out of platform flash in master serial
mode.
* I need to configure even the slave FPGA. The only non-volatile source
of its configuration data is the platform flash connected to the master
FPGA.

I used STARTUP_VIRTEX4 primitive to take control over the CCLK and DONE
signals. While generating bitstream I used the "-g DONE_cycle:KEEP"
option. From my measurements of the interface between flash and
Virtex-4, this part of the design works fine. I fully control the
signals, DONE does not go high anywhere in the middle, and flash sends
me additional bitstream data.

To access additional bitstream I instantiated the USR_ACCESS_VIRTEX4
primitive, but here is the problem. Even though I see the data on the
DIN input of the Virtex-4, the DATAVALID output of the
USR_ACCESS_VIRTEX4 primitive never goes high. So that I am unable to
reach this data inside the Virtex-4 FPGA.

The Virtex-4 Libraries Guide for HDL Design says: The PROM should
contain a packet of data with the USR_ACCESS register as the target. I
generated my PROM file using iMPACT simply putting two bitstreams into
single MCS file what is probably wrong. I think my MCS should contain
normal master FPGA bitstream followed by the slave FPGA bitsream with
target set to USR_ACCESS. Is there any way how to set target for the
second bitsream in MCS to USR_ACCESS so that I could access it from my
master FPGA?

If I am trying to do something impossible, is there another approach how
read slave configuration data from platform flash using master FPGA? I
cannot do it simply controlling flash pins, as they are not connected to
IO pins of the FPGA but to dedicated configuration pins only.

Thanks for advices,
Jan

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  #2 (permalink)  
Old 11-16-2007, 09:43 AM
Antti
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Default Re: USR_ACCESS_VIRTEX4 usage

On 14 Nov., 18:34, Jan Pech <[email protected]> wrote:
> Hello all,
>
> I would like to use the USR_ACCESS_VIRTEX4 primitive to access an
> additional bitstream stored in a config flash. The situation is
> following:
> * I have a master FPGA (Virtex-4FX) and a slave FPGA (Spartan-3A). The
> slave FPGA is located on an additional board and it is NOT daisy-chained
> with the master one.
> * Master FPGA gets configured out of platform flash in master serial
> mode.
> * I need to configure even the slave FPGA. The only non-volatile source
> of its configuration data is the platform flash connected to the master
> FPGA.
>
> I used STARTUP_VIRTEX4 primitive to take control over the CCLK and DONE
> signals. While generating bitstream I used the "-g DONE_cycle:KEEP"
> option. From my measurements of the interface between flash and
> Virtex-4, this part of the design works fine. I fully control the
> signals, DONE does not go high anywhere in the middle, and flash sends
> me additional bitstream data.
>
> To access additional bitstream I instantiated the USR_ACCESS_VIRTEX4
> primitive, but here is the problem. Even though I see the data on the
> DIN input of the Virtex-4, the DATAVALID output of the
> USR_ACCESS_VIRTEX4 primitive never goes high. So that I am unable to
> reach this data inside the Virtex-4 FPGA.
>
> The Virtex-4 Libraries Guide for HDL Design says: The PROM should
> contain a packet of data with the USR_ACCESS register as the target. I
> generated my PROM file using iMPACT simply putting two bitstreams into
> single MCS file what is probably wrong. I think my MCS should contain
> normal master FPGA bitstream followed by the slave FPGA bitsream with
> target set to USR_ACCESS. Is there any way how to set target for the
> second bitsream in MCS to USR_ACCESS so that I could access it from my
> master FPGA?
>
> If I am trying to do something impossible, is there another approach how
> read slave configuration data from platform flash using master FPGA? I
> cannot do it simply controlling flash pins, as they are not connected to
> IO pins of the FPGA but to dedicated configuration pins only.
>
> Thanks for advices,
> Jan


no no no

what you want is doable ok, but not with the tools provided by xilinx

..

you need
1) your own bit file merge tool that converts and inserts specially
formatted bitstream into master bitstream
2) your own USR_ACCESS_TO_SERCONFIG gateway IP-core that you compile
into the master FPGA

please look at ultracontroller reference designs, xilinx uses this
(very similar method) to load the PPC memories
they add the info into master bitstream and use usr_access connected
JTAG master ip core

Antti
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  #3 (permalink)  
Old 11-16-2007, 04:39 PM
Jan Pech
Guest
 
Posts: n/a
Default Re: USR_ACCESS_VIRTEX4 usage

On Fri, 2007-11-16 at 01:43 -0800, Antti wrote:
> On 14 Nov., 18:34, Jan Pech <[email protected]> wrote:
> > Hello all,
> >
> > I would like to use the USR_ACCESS_VIRTEX4 primitive to access an
> > additional bitstream stored in a config flash. The situation is
> > following:
> > * I have a master FPGA (Virtex-4FX) and a slave FPGA (Spartan-3A). The
> > slave FPGA is located on an additional board and it is NOT daisy-chained
> > with the master one.
> > * Master FPGA gets configured out of platform flash in master serial
> > mode.
> > * I need to configure even the slave FPGA. The only non-volatile source
> > of its configuration data is the platform flash connected to the master
> > FPGA.
> >
> > I used STARTUP_VIRTEX4 primitive to take control over the CCLK and DONE
> > signals. While generating bitstream I used the "-g DONE_cycle:KEEP"
> > option. From my measurements of the interface between flash and
> > Virtex-4, this part of the design works fine. I fully control the
> > signals, DONE does not go high anywhere in the middle, and flash sends
> > me additional bitstream data.
> >
> > To access additional bitstream I instantiated the USR_ACCESS_VIRTEX4
> > primitive, but here is the problem. Even though I see the data on the
> > DIN input of the Virtex-4, the DATAVALID output of the
> > USR_ACCESS_VIRTEX4 primitive never goes high. So that I am unable to
> > reach this data inside the Virtex-4 FPGA.
> >
> > The Virtex-4 Libraries Guide for HDL Design says: The PROM should
> > contain a packet of data with the USR_ACCESS register as the target. I
> > generated my PROM file using iMPACT simply putting two bitstreams into
> > single MCS file what is probably wrong. I think my MCS should contain
> > normal master FPGA bitstream followed by the slave FPGA bitsream with
> > target set to USR_ACCESS. Is there any way how to set target for the
> > second bitsream in MCS to USR_ACCESS so that I could access it from my
> > master FPGA?
> >
> > If I am trying to do something impossible, is there another approach how
> > read slave configuration data from platform flash using master FPGA? I
> > cannot do it simply controlling flash pins, as they are not connected to
> > IO pins of the FPGA but to dedicated configuration pins only.
> >
> > Thanks for advices,
> > Jan

>
> no no no
>
> what you want is doable ok, but not with the tools provided by xilinx
>
> .
>
> you need
> 1) your own bit file merge tool that converts and inserts specially
> formatted bitstream into master bitstream
> 2) your own USR_ACCESS_TO_SERCONFIG gateway IP-core that you compile
> into the master FPGA
>
> please look at ultracontroller reference designs, xilinx uses this
> (very similar method) to load the PPC memories
> they add the info into master bitstream and use usr_access connected
> JTAG master ip core
>
> Antti


Thank you Antti,

Meanwhile I solved it myself but I have forgotten to post my solution
here. I simply converted my "slave FPGA" bitstream to raw binary file
and merged it together with the "master FPGA" bitstream using Perl
script genmcs.pl from xapp719 modified according to my needs.

Converting the data itself to slave-serial configuration stream is
matter of single shift register but I spent some time with oscilloscope
to get correct bit order. Additionally, the first word I get from the
USR_ACCESS register does not belong to my "slave" configuration data so
I skip it always.

Jan

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