FPGA Central

Hi,

I would like to know if anyone has experience with connecting an
external CDR or CPA to a Virtex RocketIO MGT.

I am using the Virtex-II Pro MGTs in an optical CDMA application where
the receiver does not have the luxury of a constant flow of data. In
this application, the data arrives in irregular bursts and the rest of
the time there is no signal. The CDR built into the MGTs does not
achieve lock quickly enough to capture the data in each burst, so I am
planning to use an external clock phase aligner (CPA) such as the
MAX3634 to produce the recovered data clock.

The RocketIO Transceiver User Guide (UG024) mentions on page 109 that
the MGT CDR can "accept an external precision clock, REFCLK, which
either acts to clock incoming data or to assist in synchronizing the
derived RXRECCLK". This suggests to me that I could simply connect the
clock signal generated by the CPA as a reference clock and it could be
used to sample the incoming data. My problem is, I can't find any
information on how to select an external clock as a sampling clock for
the incoming data. There does not seem to be much information on the
built-in CDR, what parameters it has or how to change them.

I would very much appreciate some advice on this matter. Thank you.

Jeff