FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 07-14-2006, 02:10 PM
Guest
 
Posts: n/a
Default Using Samsung DDR2 memory with Xilinx Memory Interface Generator (MIG)

HI,

I have MIG 1.5 installed and want to test the K4T51083QC-ZCD5 Samsung
DDR2 chips wich reside on our FPGA prototyping board.
However it seems that MIG does not support any RAM chips beside Micron
ones.
Does anybody know if is possible to manipulte the output files to
support the chip above? Are there plans from xilinx so support
additional chips in the future? When?

Any other options? I saw a DDR controller on opencores.org but no DDR2.

Reply With Quote
  #2 (permalink)  
Old 07-14-2006, 03:01 PM
Joseph Samson
Guest
 
Posts: n/a
Default Re: Using Samsung DDR2 memory with Xilinx Memory Interface Generator(MIG)

[email protected] wrote:
> HI,
>
> I have MIG 1.5 installed and want to test the K4T51083QC-ZCD5 Samsung
> DDR2 chips wich reside on our FPGA prototyping board.
> However it seems that MIG does not support any RAM chips beside Micron
> ones.
> Does anybody know if is possible to manipulte the output files to
> support the chip above? Are there plans from xilinx so support
> additional chips in the future? When?
>
> Any other options? I saw a DDR controller on opencores.org but no DDR2.


I don't have the Samsung datasheet, but there will be a Micron
equivalent. Choose that chip when generating the MIG controller. There
will be a parameter file generated as part of the design. You can fine
tune any parameters there if needed.

If you're targeting Virtex 4, MIG1.5 DDR2 uses the FIFO16. You'll want
to fix the read/write address FIFO. I used CoreGen to make a blockram
FIFO, but Xilinx has an app note on FIFO16 workarounds. I found that
under certain conditions, the controller would have 'runaway' read
cycles, where the controller thought that the FIFO still had addressess
to read from so it would constantly read from the same location.


---
Joe Samson
Pixel Velocity
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
FPGAs and DDR2 memory Glen Gibb Verilog 0 11-13-2006 09:08 AM
DDR2 Memory Design: Layout, timing [email protected] FPGA 5 02-23-2006 02:03 PM
Xilinx V4 & DDR2 Memory Interface Enzo Guerra FPGA 2 08-07-2005 05:48 PM
Xilinx Memory Interface Generator Steve FPGA 0 02-20-2005 06:39 PM
Xilinx Memory Interface Generator Sean Durkin FPGA 0 12-03-2004 07:06 AM


All times are GMT +1. The time now is 01:06 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2019, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved