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Old 03-24-2005, 03:48 PM
hanson j
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Default using the for-loop !

Hi .. why cant i synthesize a module where i have a for-loop which runs thourgh a signal std_logic_vector data_in ....

for I in 0 to 31 loop if data_in(I)='1' then // do stuff end loop

xilinx just runs forever .. never finishing ... but if i declare the std_logic_vector to be a constant instead of a signal then i works :/

What could be the reason
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